Abstract: A phased array system has a substrate, a plurality of elements, a beamforming IC, and a plurality of feedlines electrically coupling the plurality of elements with at least one beamforming IC. In preferred embodiments, the feedlines are non-intersecting, symmetric feedlines that mitigate cross-polarization.

Abstract: Exemplary embodiments include RF integrated circuit (RFIC) chips including programmable on-chip element swapping circuitry, channel swapping circuitry, and/or phase rotation circuitry to allow a common software implementation or parameter computation to be used across multiple products having different arrangements and orientations of RFICs and elements.

Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using interpolation and a look-up table for calculation of phase setting values such as for fast beam steering.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: A patch array has a routing printed circuit board with a plurality of layers for routing signals, and a plurality of printed circuit board patches that each has at least one through-via. The plurality of patches are mounted with the routing printed circuit board. In addition, the plurality of printed circuit board patches are formed in compliance with standard printed circuit board rules.

Abstract: A symmetric, multi-layer, three-way power divider that is equally balanced, with resistors placed between all combinations of legs. This three-way power divider is specifically designed to be used in millimeter wave applications (e.g., 5G in the 20 GHz-40 GHz range for both dual and single polarization), specifically in designs where a common signal is distributed to a multiple of three elements. This three-way power divider also can be useful for addressing space constraints in 5G applications, e.g., due to routing limitations.

Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.

Abstract: A selective calibration system for signal processing integrated circuits includes a calibration information generator that receives information identifying a group of signal processing integrated circuits associated with a product, the group of signal processing integrated circuits being a subset of a population of signal processing integrated circuits for which performance information is stored, and uses the performance information to produce calibration information for the identified signal processing integrated circuits as a group. The calibration information generator generally uses only performance information associated with the identified signal processing integrated circuits to produce the calibration information so that each signal processing integrated circuit in the group is calibrated relative to just that group of signal processing integrated circuits. Direct product access to the calibration information generator can be provided.

Abstract: A symmetric, multi-layer, three-way power divider that is equally balanced, with resistors placed between all combinations of legs. This three-way power divider is specifically designed to be used in millimeter wave applications (e.g., 5G in the 20 GHz-40 GHz range for both dual and single polarization), specifically in designs where a common signal is distributed to a multiple of three elements. This three-way power divider also can be useful for addressing space constraints in 5G applications, e.g., due to routing limitations.