Abstract: A decoder for decoding a plurality of digital video data is described. In an embodiment, the decoder comprises a DV video decoder for decoding digital video data which is formatted according to the DV standard. The DV video decoder has a Very-Long Instruction Word (VLIW) processor and a variable length decoding unit. The VLIW processor includes a preparser unit for recovering a decoding order of the digital video data so that the variable length decoding unit can process the digital video data. The variable length decoding unit decodes a variable length coding format of the digital video data which has been preparsed by the VLIW processor. Furthermore, the VLIW processor includes a decompression unit for decompressing the digital video data which has been decoded by the variable length decoding unit. In an embodiment, the VLIW processor and the variable length decoding unit are formed on the same semiconductor device.

Abstract: Methods and systems are disclosed for decoding image data including I-picture, P-picture, and B-picture encoded data. A method includes receiving encoded image data and selectively performing a modified inverse discrete cosine transform (IDCT) process to generate output pixel array blocks at a lower resolution than the resolution of the received image data. The image data can be 8×8 pixel array blocks, which are used to produce lower resolution pixel array blocks such as, for example, 4×8 or 4×4 pixel array blocks. In certain instances, after the IDCT process is performed, the resulting pixel data is up-sampled before motion compensation is performed. Furthermore, in certain instances, the resulting pixel data is subjected to motion compensation and scaled to display size prior to display.

Abstract: Methods and systems are disclosed for decoding image data including I-picture, P-picture, and B-picture encoded data. A method includes receiving encoded image data and selectively performing a modified inverse discrete cosine transform (IDCT) process to generate output pixel array blocks at a lower resolution than the resolution of the received image data. The image data can be 8×8 pixel array blocks, which are used to produce lower resolution pixel array blocks such as, for example, 4×8 or 4×4 pixel array blocks. In certain instances, after the IDCT process is performed, the resulting pixel data is up-sampled before motion compensation is performed. Furthermore, in certain instances, the resulting pixel data is subjected to motion compensation and scaled to display size prior to display.

Abstract: Methods and systems are disclosed for decoding image data including I-picture, P-picture, and B-picture encoded data. A method includes receiving encoded image data and selectively performing a modified inverse discrete cosine transform (IDCT) process to generate output pixel array blocks at a lower resolution than the resolution of the received image data. The image data can be 8×8 pixel array blocks, which are used to produce lower resolution pixel array blocks such as, for example, 4×8 or 4×4 pixel array blocks. In certain instances, after the IDCT process is performed, the resulting pixel data is up-sampled before motion compensation is performed. Furthermore, in certain instances, the resulting pixel data is subjected to motion compensation and scaled to display size prior to display.

Abstract: A decoder for decoding a plurality of digital video data is described. In an embodiment, the decoder comprises a DV video decoder for decoding digital video data which is formatted according to the DV standard. The DV video decoder has a Very-Long Instruction Word (VLIW) processor and a variable length decoding unit. The VLIW processor includes a preparser unit for recovering a decoding order of the digital video data so that the variable length decoding unit can process the digital video data. The variable length decoding unit decodes a variable length coding format of the digital video data which has been preparsed by the VLIW processor. Furthermore, the VLIW processor includes a decompression unit for decompressing the digital video data which has been decoded by the variable length decoding unit. In an embodiment, the VLIW processor and the variable length decoding unit are formed on the same semiconductor device.

Abstract: System and method for balancing video encoding tasks between multiple processors. The method may include receiving a real time video stream, performing picture level and upper processing on a main processor, executing a macroblock loop in parallel on a main processor and a co-processor, wherein executing includes processing a first group of video encoding tasks on the main processor and processing a second group of video encoding tasks on the co-processor, and outputting an encoded version of the real time broadcast. The method may be implemented on a system that includes a main processor, a co-processor, and an interface to receive the real time video stream, each coupled to one or more buses. The encoding may be performed according to the well known Moving Pictures Experts Group (MPEG) standards.

Abstract: A decoder for decoding a plurality of digital video data is described. In an embodiment, the decoder comprises a DV video decoder for decoding digital video data which is formatted according to the DV standard. The DV video decoder has a Very-Long Instruction Word (VLIW) processor and a variable length decoding unit. The VLIW processor includes a preparser unit for recovering a decoding order of the digital video data so that the variable length decoding unit can process the digital video data. The variable length decoding unit decodes a variable length coding format of the digital video data which has been preparsed by the VLIW processor. Furthermore, the VLIW processor includes a decompression unit for decompressing the digital video data which has been decoded by the variable length decoding unit. In an embodiment, the VLIW processor and the variable length decoding unit are formed on the same semiconductor device.

Abstract: A method and system for decoding symbols of variable length in a digital video bit stream in real time, using Very Long Instruction Word (VLIW) architecture. In one embodiment, several bit sections are first read from a bit stream. While the first bit section will correspond to a valid symbol in the bit-stream, the rest of the bit sections may or may not, depending on the length of the first section. A table of variable length codes is then indexed to obtain a look-up result for each of the read-in bit sections, which done in parallel for all sections. Next, a determination is made as to whether each of the look-up results is valid. A valid look-up result provides the length of the symbol. The valid look-up values are then accepted. In another embodiment the bit stream is thereafter advanced by the sum of all accepted look-up results.

Abstract: A method and system for decoding symbols of variable length in a digital video bit stream in real time, using Very Long Instruction Word (VLIW) architecture. One embodiment of the present invention first reads several bit sections from a bit stream. The bit stream comprises digital video information and is made up of a series of encoded symbols of varying length. While the first bit section will correspond to a valid symbol in the bit-stream, the rest of the bit sections may or may not, depending on the length of the first section. The next step of this embodiment is indexing a table of variable length codes to obtain a look-up result for each of the read-in bit sections. This is done in parallel for all sections. Next, this embodiment of the present invention determines whether each of the look-up results is valid. A valid look-up result provides the length of the symbol. Next, the valid look-up values are accepted.

Abstract: In methods and systems consistent with the present invention, the process of inverse quantization is performed by determining class number and quantization number for each block of received quantized DCT coefficients, determining a first shift value based on the class number and quantization number and a second shift value based on the class number and a combination type, and shifting the entire block of DCT coefficients based on the first and second shift values. Alternatively, the inverse quantization may be combined with inverse weighting step by pre-shifting a set of weighting tables, one for each area number combination. A pre-shifted weighting matrix is then selected based on the second shift value and multiplied by the shifted matrix of DCT coefficients. In another embodiment, a pre-shifted weighting table is selected based on the class number and combination type and then multiplied by the shifted matrix of DCT coefficients.

Abstract: A multiple symbol length lookup table is described. The multiple symbol length lookup table includes a plurality of lookup entries and a plurality of lookup results, each lookup entry having a corresponding lookup result. Each lookup entry comprises a particular sequence of input data bits. The input data bits are encoded with a variable length coding. Moreover, the input data bits form one or more consecutive variable length symbols. Each lookup result comprises a total length of the consecutive variable length symbols in the input data bits. In an embodiment, the multiple symbol length lookup table is generated by using a single symbol length lookup table. In practice, the input data bits are submitted to the multiple symbol length lookup table as a lookup entry. In response, the multiple symbol length lookup table returns a lookup result that is the total length or number of bits in the input data bits that a variable length decoder can decode.

Abstract: A multiple symbol length lookup table is described. The multiple symbol length lookup table includes a plurality of lookup entries and a plurality of lookup results, each lookup entry having a corresponding lookup result. Each lookup entry comprises a particular sequence of input data bits. The input data bits are encoded with a variable length coding. Moreover, the input data bits form one or more consecutive variable length symbols. Each lookup result comprises a total length of the consecutive variable length symbols in the input data bits. In an embodiment, the multiple symbol length lookup table is generated by using a single symbol length lookup table. In practice, the input data bits are submitted to the multiple symbol length lookup table as a lookup entry. In response, the multiple symbol length lookup table returns a lookup result that is the total length or number of bits in the input data bits that a variable length decoder can decode.

Abstract: System and method for balancing video encoding tasks between multiple processors. The method may include receiving a real time video stream, performing picture level and upper processing on a main processor, executing a macroblock loop in parallel on a main processor and a co-processor, wherein executing includes processing a first group of video encoding tasks on the main processor and processing a second group of video encoding tasks on the co-processor, and outputting an encoded version of the real time broadcast. The method may be implemented on a system that includes a main processor, a co-processor, and an interface to receive the real time video stream, each coupled to one or more buses. The encoding may be performed according to the well known Moving Pictures Experts Group (MPEG) standards.

Abstract: A system and method for performing a coefficient reconstruction in a decoder. The method comprises receiving a transmitted coefficient of a first block. The method also comprises retrieving a former reconstructed value. Additionally, the method comprises executing a first arithmetic operation to generate a reconstructed value of the transmitted coefficient. The first arithmetic operation is performed using the transmitted coefficient and the former reconstructed value. Finally, the method comprises replacing the former reconstructed value with the new reconstructed value.

Abstract: In methods and systems consistent with the present invention, the process of inverse quantization is performed by determining class number and quantization number for each block of received quantized DCT coefficients, determining a first shift value based on the class number and quantization number and a second shift value based on the class number and a combination type, and shifting the entire block of DCT coefficients based on the first and second shift values. Alternatively, the inverse quantization may be combined with inverse weighting step by pre-shifting a set of weighting tables, one for each area number combination. A pre-shifted weighting matrix is then selected based on the second shift value and multiplied by the shifted matrix of DCT coefficients. In another embodiment, a pre-shifted weighting table is selected based on the class number and combination type and then multiplied by the shifted matrix of DCT coefficients.

Abstract: A variable length code decoder includes modified VLC decode tables as compared to table b.14 and b.15 of Annex B of the ISO/IEC 31818-2 standard, and improved program code for inverse quantising block DCT coefficients. The modified VLC decoding tables include level values corresponding to VLC coded words that have been pre-multiplied by the value 2, or by 2 then plus 1. As a result, the modified tables of the present invention reduces the computational complexity of the inverse quantization calculation of the method of the present invention as compared to the algorithm provided in ISO/IEC 31818-2, section 7. Advantageously, the bandwidth requirement of the inverse quantiser processor is reduced as compared to the bandwidth requirement of an inverse processor executing the inverse quantization calculation as defined in the Standard. Conveniently, lower cost, and more widely available processors may be used in the decoder of the present invention.