Patents by Inventor Jason Panavich
Jason Panavich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11372757Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: GrantFiled: September 4, 2020Date of Patent: June 28, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael B. Mitchell, Michael P. Wilson
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Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devices
Patent number: 11354239Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: GrantFiled: September 18, 2020Date of Patent: June 7, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Kevin Neal Magill, Jason Panavich, Derek Bachand, Michael B. Mitchell, Michael P. Wilson -
MAINTAINING DOMAIN COHERENCE STATES INCLUDING DOMAIN STATE NO-OWNED (DSN) IN PROCESSOR-BASED DEVICES
Publication number: 20220091979Abstract: Maintaining domain coherence states including Domain State No-Owned (DSN) in processor-based devices is disclosed. In this regard, a processor-based device provides multiple processing elements (PEs) organized into multiple domains, each containing one or more PEs and a local ordering point circuit (LOP). The processor-based device supports domain coherence states for coherence granules cached by the PEs within a given domain. The domain coherence states include a DSN domain coherence state, which indicates that a coherence granule is not cached within a shared modified state within any domain. In some embodiments, upon receiving a request for a read access to a coherence granule, a system ordering point circuit (SOP) determines that the coherence granule is cached in the DSN domain coherence state within a domain of the plurality of domains, and can safely read the coherence granule from the system memory to satisfy the read access if necessary.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Eric Francis ROBINSON, Kevin Neal MAGILL, Jason PANAVICH, Derek BACHAND, Michael B. MITCHELL, Michael P. WILSON -
Publication number: 20220075726Abstract: Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) and a central ordering point circuit (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation. The COP's selection is based on protocol preference indicators generated by the PEs using repeat-read indicators that each PE maintains to track whether a coherence granule was repeatedly read by the PE (e.g., as a result of polling reads, or as a result of re-reading the coherence granule after it was evicted from a cache due to an invalidating snoop). After selecting the cache coherence protocol, the COP sends a response message to the PEs indicating the selected cache coherence protocol.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 11138114Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: GrantFiled: January 8, 2020Date of Patent: October 5, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Kevin Neal Magill, Eric Francis Robinson, Derek Bachand, Jason Panavich, Michael P. Wilson, Michael B. Mitchell
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Patent number: 11093396Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: GrantFiled: November 8, 2019Date of Patent: August 17, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Derek Bachand, Jason Panavich, Kevin Neal Magill, Michael B. Mitchell, Michael P. Wilson
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Publication number: 20210209026Abstract: Providing dynamic selection of cache coherence protocols in processor-based devices is disclosed. In this regard, a processor-based device includes a master PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write invalidate protocol or a write update protocol as a cache coherence protocol to use for maintaining cache coherency for a memory store operation by the master PE. The selection is made by the COP based on one or more protocol preference indicators that may be generated and provided by one or more of the master PE, the at least one snooper PE, and the COP itself. After selecting the cache coherence protocol to use, the COP sends a response message to each of the master PE and the at least one snooper PE indicating the selected cache coherence protocol.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: Kevin Neal MAGILL, Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Michael P. WILSON, Michael B. MITCHELL
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Publication number: 20210141726Abstract: Enabling atomic memory accesses across coherence granule boundaries in processor-based devices is disclosed. In this regard, a processor-based device includes multiple processing elements (PEs), and further includes a special-purpose central ordering point (SPCOP) configured to distribute coherence granule (“cogran”) pair atomic access (CPAA) tokens. To perform an atomic memory access on a pair of coherence granules, a PE must hold a CPAA token for an address block containing one of the pair of coherence granules before the PE can obtain each of the pair of coherence granules in an exclusive state. Because a CPAA token must be acquired before obtaining exclusive access to at least one of the pair of coherence granules, and because the SPCOP is configured to allow only one CPAA token to be active for a given address block, deadlocks and livelocks between PEs seeking to access the same coherence granules can be avoided.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventors: Eric Francis ROBINSON, Derek BACHAND, Jason PANAVICH, Kevin Neal MAGILL, Michael B. MITCHELL, Michael P. WILSON
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Patent number: 10896135Abstract: Facilitating page table entry (PTE) maintenance in processor-based devices is disclosed. In this regard, a processor-based device includes processing elements (PEs) configured to support two new coherence states: walker-readable (W) and modified walker accessible (MW). The W coherence state indicates that read access to a corresponding coherence granule by hardware table walkers (HTWs) is permitted, but all write operations and all read operations by non-HTW agents are disallowed. The MW coherence state indicates that cached copies of the coherence granule visible only to HTWs may exist in other caches. In some embodiments, each PE is also configured to support a special page table entry (SP-PTE) field store instruction for modifying SP-PTE fields of a PTE, indicating to the PE's local cache that the corresponding coherence granule should transition to the MW state, and indicating to remote local caches that copies of the coherence granule should update their coherence state.Type: GrantFiled: September 3, 2019Date of Patent: January 19, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Eric Francis Robinson, Jason Panavich, Thomas Philip Speier
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Patent number: 6931498Abstract: A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.Type: GrantFiled: April 3, 2001Date of Patent: August 16, 2005Assignee: Intel CorporationInventors: Sanjay S. Talreja, Jason Panavich, Ramkarthik Ganesan, Terry L. Kendall
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Publication number: 20020144066Abstract: A single status register, capable of providing status for simultaneous read-while-write operation on a flash memory array is described. The status of the memory array is reported to the user based on two partitions. A microcontroller is used to traffic the status register to memory array communication.Type: ApplicationFiled: April 3, 2001Publication date: October 3, 2002Inventors: Sanjay S. Talreja, Jason Panavich, Ramkarthik Ganesan, Terry L. Kendall