Patents by Inventor Jason PLANT

Jason PLANT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133501
    Abstract: Pipe plugs can be used to minimize or eliminate contamination of pipes before they are installed. A pipe plug can include a body that is enclosed at a rear end and that forms a flange at a front end. The flange can be sized to cover an opening of a pipe in which the body of the pipe plug is inserted. The body can include fins that extend outwardly from an outer surface of the body to apply a retaining force against the pipe. One or more tabs can extend outwardly beyond the flange to facilitate removing the pipe plug from the pipe.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Jason Plant, R. Jason Barnes
  • Patent number: 11948300
    Abstract: Machine learning systems and methods are disclosed for prediction of wound healing, such as for diabetic foot ulcers or other wounds, and for assessment implementations such as segmentation of images into wound regions and non-wound regions. Systems for assessing or predicting wound healing can include a light detection element configured to collect light of at least a first wavelength reflected from a tissue region including a wound, and one or more processors configured to generate an image based on a signal from the light detection element having pixels depicting the tissue region, determine reflectance intensity values for at least a subset of the pixels, determine one or more quantitative features of the subset of the plurality of pixels based on the reflectance intensity values, and generate a predicted or assessed healing parameter associated with the wound over a predetermined time interval.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: April 2, 2024
    Assignee: Spectral MD, Inc.
    Inventors: Wensheng Fan, John Michael DiMaio, Jeffrey E. Thatcher, Peiran Quan, Faliu Yi, Kevin Plant, Ronald Baxter, Brian McCall, Zhicun Gao, Jason Dwight
  • Publication number: 20230400652
    Abstract: A III-V/SiNx hybrid integrated photonics platform is described. A wafer can include regions where SiNx waveguides are formed and regions where III-V waveguides have been grown heteroepitaxially from the Si substrate and formed lithographically to butt couple to the SiNx waveguides. Efficient optical coupling is possible between the SiNx and III-V waveguides (?2.5 dB loss/transition). A threading dislocation density (TDD) as low as 4×106 cm?2 can be obtained in the III-V waveguides. The TDD enables fully parallel fabrication of integrated III-V optoelectronic devices, allowing for complex photonic integrated circuits with many active components.
    Type: Application
    Filed: May 15, 2023
    Publication date: December 14, 2023
    Inventors: Christopher Heidelberger, Cheryl Marie SORACE-AGASKAR, Jason PLANT, Boris KHARAS, Reuel B. SWINT, Yifei Li, Paul William JUODAWLKIS
  • Patent number: 11340400
    Abstract: Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 24, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Boris Kharas, Reuel B. Swint, Cheryl Marie Sorace-Agaskar, Paul William Juodawlkis, Suraj Deepak Bramhavar, Jason Plant
  • Publication number: 20200284978
    Abstract: Photonic integrated circuits (PICs) enable manipulation of light on a chip for telecommunications and information processing. They can be made with silicon and silicon-compatible materials using complementary metal-oxide-semiconductor (CMOS) fabrication techniques developed for making electronics. Unfortunately, most light sources are made with III-V and II-VI materials, which are not compatible with silicon CMOS fabrication techniques. As a result, the light source for a PIC is either off-chip or integrated onto the PIC after CMOS fabrication is over. Hybrid integration can be improved by forming a recess in the PIC to receive a III-V or II-VI photonic chip. Mechanical stops formed in or next to the recess during fabrication align the photonic chip vertically to the PIC. Fiducials on the PIC and the photonic chip enable sub-micron lateral alignment. As a result, the photonic chip can be flip-chip bonded to the PIC with sub-micron vertical and lateral alignment precision.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 10, 2020
    Inventors: Boris KHARAS, Reuel B. SWINT, Cheryl Marie SORACE-AGASKAR, Paul William JUODAWLKIS, Suraj Deepak BRAMHAVAR, Jason PLANT