Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.

Abstract: Guided-wave photodetectors based on absorption of infrared photons by mid-bandgap states in non-crystal semiconductors. In one example, a resonant guided-wave photodetector is fabricated based on a polysilicon layer used for the transistor gate in a SOI CMOS process without any change to the foundry process flow (‘zero-change’ CMOS). Mid-bandgap defect states in the polysilicon absorb infrared photons. Through a combination of doping mask layers, a lateral p-n junction is formed in the polysilicon, and a bias voltage applied across the junction creates a sufficiently strong electric field to enable efficient photo-generated carrier extraction and high-speed operation. An example device has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.

Abstract: Devices and techniques for integrated optical data communication. A method of encoding symbols in an optical signal may include encoding a first symbol by injecting charge carriers, at a first rate, into a semiconductor device, such as a PIN diode. The method may also include encoding a second symbol by injecting charge carriers, at a second rate, into the semiconductor device. The first rate may exceed the second rate. A modulator driver circuit may include a resistive circuit coupled between supply terminal and drive terminals. The modulator driver circuit may also include a control circuit coupled between a data terminal and the resistive circuit. The control circuit may modulate a resistance of the resistive circuit by selectively coupling one or more of a plurality of portions of the resistive circuit to the drive terminal based on data to be optically encoded.

Abstract: Devices and techniques for integrated optical data communication. An optical receiver may include a photodetector and a differential amplifier. The photodetector is coupled to an optical waveguide. The optical waveguide is configured to provide an optical signal encoding data. A first terminal of the differential amplifier is coupled to receive a photodetection signal from the photodetector. A second terminal of the differential amplifier is coupled to receive, from a noise measurement unit, a reference signal representing a noise component of the photodetection signal. The differential amplifier is configured to provide an amplifier signal encoding at least some of the data.

Abstract: Conventional approaches to integrating waveguides within standard electronic processes typically involve using a dielectric layer, such as polysilicon, single-crystalline silicon, or silicon nitride, within the in-foundry process or depositing and patterning a dielectric layer in the backend as a post-foundry process. In the present approach, the back-end of the silicon handle is etched away after in-foundry processing to expose voids or trenches defined using standard in-foundry processing (e.g., complementary metal-oxide-semiconductor (CMOS) processing). Depositing dielectric material into a void or trench yields an optical waveguide integrated within the front-end of the wafer. For example, a shallow trench isolation (STI) layer formed in-foundry may serve as a high-resolution patterning waveguide template in a damascene process within the front end of a die or wafer.