Patents by Inventor Jason T. Jones
Jason T. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240126560Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Inventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A.T. Jones, Jayant Thakur
-
Patent number: 11960416Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.Type: GrantFiled: December 21, 2021Date of Patent: April 16, 2024Assignee: Texas Instruments IncorporatedInventors: Daniel Brad Wu, Abhishek Shankar, Mihir Narendra Mody, Gregory Raymond Shurtz, Jason A. T. Jones, Hemant Vijay Kumar Hariyani
-
Patent number: 11880333Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).Type: GrantFiled: May 7, 2021Date of Patent: January 23, 2024Assignee: Texas Instruments IncorporatedInventors: Jason A. T. Jones, Sriramakrishnan Govindarajan, Mihir Narendra Mody, Kishon Vijay Abraham Israel Vijayponraj, Bradley Douglas Cobb, Sanand Prasad, Gregory Raymond Shurtz, Martin Jeffrey Ambrose, Jayant Thakur
-
Patent number: 11853772Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: GrantFiled: August 16, 2022Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A. T. Jones, Jayant Thakur
-
Publication number: 20230350811Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Sriramakrishnan GOVINDARAJAN, Gregory Raymond SHURTZ, Mihir Narendra MODY, Charles Lance FUOCO, Donald E. STEISS, Jonathan Elliot BERGSAGEL, Jason A.T. JONES
-
Publication number: 20230326002Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.Type: ApplicationFiled: June 12, 2023Publication date: October 12, 2023Inventors: Mihir Narendra MODY, JR., Veeramanikandan RAJU, Niraj NANDAN, Samuel Paul VISALLI, Jason A.T. JONES, Kedar Satish CHITNIS, Gregory Raymond SHURTZ, Prithvi Shankar YEYYADI ANANTHA, Sriramakrishnan GOVINDARAJAN
-
Patent number: 11715188Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.Type: GrantFiled: February 28, 2022Date of Patent: August 1, 2023Assignee: Texas Instruments IncorporatedInventors: Mihir Narendra Mody, Veeramanikandan Raju, Niraj Nandan, Samuel Paul Visalli, Jason A. T. Jones, Kedar Satish Chitnis, Gregory Raymond Shurtz, Prithvi Shankar Yeyyadi Anantha, Sriramakrishnan Govindarajan
-
Patent number: 11704391Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.Type: GrantFiled: September 28, 2021Date of Patent: July 18, 2023Assignee: Texas Instruments IncorporatedInventors: Deepak Kumar Poddar, Mihir Mody, Veeramanikandan Raju, Jason A. T. Jones
-
Publication number: 20230222072Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.Type: ApplicationFiled: March 20, 2023Publication date: July 13, 2023Inventors: Sriramakrishnan GOVINDARAJAN, Kishon Vijay Abraham ISRAEL VIJAYPONRAJ, Mihir Narendra MODY, Jason A.T. Jones
-
Patent number: 11693787Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.Type: GrantFiled: February 9, 2021Date of Patent: July 4, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Gregory Raymond Shurtz, Mihir Narendra Mody, Charles Lance Fuoco, Donald E. Steiss, Jonathan Elliot Bergsagel, Jason A.T. Jones
-
Publication number: 20230195658Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Daniel Brad WU, Abhishek SHANKAR, Mihir Narendra MODY, Gregory Raymond SHURTZ, Jason A. T. JONES, Hemant Vijay Kumar HARIYANI
-
Patent number: 11609866Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.Type: GrantFiled: October 19, 2020Date of Patent: March 21, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Kishon Vijay Abraham Israel Vijayponraj, Mihir Narendra Mody, Jason A. T. Jones
-
Patent number: 11551399Abstract: Methods, apparatus, systems and articles of manufacture to perform graphics processing on combinations of graphic processing units and digital signal processors are disclosed. A disclosed example method includes processing first data representing input vertices to create second data, the first data using a first format organized by vertex, the second data using a second format organized by components of the vertices. A digital signal processor (DSP) is to perform vertex shading on the second data to create third data, the third data formatted using the second format, the vertex shading performed by executing a first instruction at the DSP, the first instruction generated based on a second instruction capable of being executed at a graphics processing unit (GPU). The third data is processed to create fourth data, the fourth data formatted using the first format.Type: GrantFiled: September 9, 2020Date of Patent: January 10, 2023Assignee: Texas Instruments IncorporatedInventors: Mihir Narendra Mody, Ajay Jayaraj, Hemant Hariyani, Anand Balagopalakrishnan, Jason A. T. Jones, Erick Zadiel Narvaez
-
Publication number: 20230004855Abstract: Techniques for executing machine learning (ML) models including receiving an indication to execute an ML model on a processing core; determining a resource allocation for executing the ML model on the processing core; determining that a layer of the ML model will use a first amount of the resource, wherein the first amount is more than an amount of the resource allocated; determining that an adaptation may be applied to executing the layer of the ML model; executing the layer of the ML model using the adaptation, wherein executing the layer using the adaptation reduces the first amount of the resource used by the layer as compared to executing the layer without using the adaptation; and outputting a result of the ML model based on the executed layer.Type: ApplicationFiled: June 30, 2021Publication date: January 5, 2023Inventors: Mihir Narendra MODY, Kumar DESAPPAN, Gregory Raymond SHURTZ, Jason A.T. JONES
-
Publication number: 20220391219Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Inventors: Sriramakrishnan GOVINDARAJAN, Denis Roland BEAUDOIN, Gregory Raymond SHURTZ, Santhanakrishnan Badri NARAYANAN, Mark Adrian BRYANS, Mihir Narendra MODY, Jason A.T. JONES, Jayant THAKUR
-
Patent number: 11436024Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: GrantFiled: December 2, 2019Date of Patent: September 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A. T. Jones, Jayant Thakur
-
Publication number: 20220114120Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Mihir MODY, Niraj NANDAN, Hetul SANGHVI, Brian CHAE, Rajasekhar Reddy ALLU, Jason A.T. JONES, Anthony LELL, Anish REGHUNATH
-
Publication number: 20220101083Abstract: Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Inventors: Mihir Narendra Mody, Shyam Jagannathan, Manu Mathew, Jason T. Jones
-
Patent number: 11237991Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.Type: GrantFiled: August 17, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mihir Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu, Jason A. T. Jones, Anthony Lell, Anish Reghunath
-
Publication number: 20220012312Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Inventors: Deepak Kumar PODDAR, Mihir MODY, Veeramanikandan RAJU, Jason A.T. JONES