Patents by Inventor Jason Vincent Bellorado
Jason Vincent Bellorado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10790933Abstract: Systems and methods are disclosed for constrained receiver parameter optimization. Two parameter optimization functions may be applied, with one function providing constraints on the results of the second function in order to determine a parameter set to apply in the receiver. A method may comprise determining a first parameter set based on a first function, determining a second parameter set based on a second function different from the first function, and determining a third parameter set by using the first parameter set to define a subset of a parameter space to which to limit values from the second parameter set. In certain embodiments, a least squares function may be used to constrain the results of a general cost function.Type: GrantFiled: June 27, 2019Date of Patent: September 29, 2020Assignee: Seagate Technology LLCInventors: Vincent Brendan Ashe, Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10692527Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.Type: GrantFiled: December 5, 2018Date of Patent: June 23, 2020Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10694007Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.Type: GrantFiled: April 1, 2019Date of Patent: June 23, 2020Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10608808Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.Type: GrantFiled: September 18, 2018Date of Patent: March 31, 2020Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10601617Abstract: A method may generate a demodulated sine component for a sequence of samples of a servo burst window of a position error signal using a sine weight look up table and generate a demodulated cosine component for the sequence of samples of the servo burst window of the position error signal using a cosine weight look up table. The sine weight and the cosine weight look up tables may have indexes representing a phase range. The method may generate a demodulated phase component signal and a demodulated amplitude component signal for the sequence of samples of the servo burst window of the position error signal based on the demodulated sine component and the demodulated cosine component using a Coordinate Rotation Digital Computer at least in part by iteratively rotating a vector based on the demodulated sine component and the demodulated cosine component and summing angular changes in the vector.Type: GrantFiled: May 8, 2018Date of Patent: March 24, 2020Assignee: Seagate Technology LLCInventors: Marcus Marrow, Jason Vincent Bellorado, Trung Thuc Nguyen
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Patent number: 10483999Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.Type: GrantFiled: June 4, 2018Date of Patent: November 19, 2019Assignee: Seagate Technology LLCInventors: Zheng Wu, Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10382166Abstract: Systems and methods are disclosed for constrained receiver parameter optimization. Two parameter optimization functions may be applied, with one function providing constraints on the results of the second function in order to determine a parameter set to apply in the receiver. A method may comprise determining a first parameter set based on a first function, determining a second parameter set based on a second function different from the first function, and determining a third parameter set by using the first parameter set to define a subset of a parameter space to which to limit values from the second parameter set. In certain embodiments, a least squares function may be used to constrain the results of a general cost function.Type: GrantFiled: February 22, 2017Date of Patent: August 13, 2019Assignee: Seagate Technology LLCInventors: Vincent Brendan Ashe, Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10298240Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.Type: GrantFiled: April 11, 2018Date of Patent: May 21, 2019Assignee: Seagate Technology LLCInventors: Marcus Marrow, Kenneth John Evans, Jason Vincent Bellorado
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Patent number: 10277718Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.Type: GrantFiled: November 22, 2016Date of Patent: April 30, 2019Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10243703Abstract: Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.Type: GrantFiled: November 13, 2017Date of Patent: March 26, 2019Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow
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Patent number: 10164760Abstract: Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.Type: GrantFiled: October 18, 2016Date of Patent: December 25, 2018Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10152457Abstract: An apparatus may include a circuit including a filter configured to update one or more adaptive coefficients of the filter based on an error signal. Further, the circuit may update a constrained coefficient of the filter based on the one or more adaptive coefficients, the constrained coefficient and a desired value. Moreover, the circuit may generate a sample of a sample sequence based on the one or more adaptive coefficients and the updated constrained coefficient, the error signal being based on the sample sequence.Type: GrantFiled: October 25, 2016Date of Patent: December 11, 2018Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 10084553Abstract: In certain embodiments, a method may include receiving one or more equalized samples of an input signal. The method may further include mitigating one or more excursions in the one or more equalized samples based on one or more current decisions of an iterative decoding process to generate compensated equalized samples. In addition, the method may include performing iterative decoding operations based on the compensated equalized samples, updating the current decisions of the iterative decoding process and outputting the current decisions as a converged result when the iterative decoding operations have converged for the compensated equalized samples.Type: GrantFiled: December 22, 2016Date of Patent: September 25, 2018Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow, Zheng Wu
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Patent number: 9998136Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.Type: GrantFiled: February 17, 2017Date of Patent: June 12, 2018Assignee: Seagate Technology LLCInventors: Zheng Wu, Jason Vincent Bellorado, Marcus Marrow
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Patent number: 9979573Abstract: A method may generate a demodulated sine component for a sequence of samples of a servo burst window of a position error signal using a sine weight look up table and generate a demodulated cosine component for the sequence of samples of the servo burst window of the position error signal using a cosine weight look up table. The sine weight and the cosine weight look up tables may have indexes representing a phase range. The method may generate a demodulated phase component signal and a demodulated amplitude component signal for the sequence of samples of the servo burst window of the position error signal based on the demodulated sine component and the demodulated cosine component using a Coordinate Rotation Digital Computer at least in part by iteratively rotating a vector based on the demodulated sine component and the demodulated cosine component and summing angular changes in the vector.Type: GrantFiled: December 23, 2016Date of Patent: May 22, 2018Assignee: Seagate Technology LLCInventors: Marcus Marrow, Jason Vincent Bellorado, Trung Thuc Nguyen
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Patent number: 9954537Abstract: In certain embodiments, an apparatus may comprise a circuit configured to scale a phase control value from an external phase control resolution of an external clock frequency to an internal phase control resolution of an internal clock frequency to generate a target phase control value. The circuit may also determine a difference between a current phase control value and the target phase control value and determine a phase step value based on the difference. Further, the circuit may modify a current phase control value based on the phase step value and generate a phase controlled clock signal at the internal clock frequency using the modified phase control value. Additionally, the circuit may divide the phase controlled clock signal at the internal clock frequency to generate a phase controlled clock signal at the external clock frequency.Type: GrantFiled: December 23, 2016Date of Patent: April 24, 2018Assignee: Seagate Technology LLCInventors: Marcus Marrow, Kenneth John Evans, Jason Vincent Bellorado
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Patent number: 9819456Abstract: Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.Type: GrantFiled: October 17, 2016Date of Patent: November 14, 2017Assignee: Seagate Technology LLCInventors: Jason Vincent Bellorado, Marcus Marrow
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Patent number: 8687672Abstract: A technique for reducing interference between a direct-sequence ultra-wideband communications system and a narrowband communications system uses interference-rejecting spreading codes to reduce signal power in a frequency band associated with the narrowband communications system. A method of operating an ultra-wideband communications system includes applying an interference-rejecting spreading code to a signal for transmission. The interference-rejecting spreading code is configured to reduce power in a particular frequency band of a transmit or receive power spectral density associated with the ultra-wideband signal without substantially reducing power outside that particular frequency band of the transmit or receive power spectral density associated with the ultra-wideband signal.Type: GrantFiled: March 22, 2013Date of Patent: April 1, 2014Assignee: AT&T Intellectual Property I, L.P.Inventors: Saeed S. Ghassemzadeh, Jason Vincent Bellorado, Ashley B. Tarokh
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Patent number: 8406278Abstract: A technique for reducing interference between a direct-sequence ultra-wideband communications system and a narrowband communications system uses interference-rejecting spreading codes to reduce signal power in a frequency band associated with the narrowband communications system. A method of operating an ultra-wideband communications system includes applying an interference-rejecting spreading code to a signal for transmission. The interference-rejecting spreading code is configured to reduce power in a particular frequency band of a transmit or receive power spectral density associated with the ultra-wideband signal without substantially reducing power outside that particular frequency band of the transmit or receive power spectral density associated with the ultra-wideband signal.Type: GrantFiled: November 20, 2009Date of Patent: March 26, 2013Assignee: AT&T Intellectual Property I, L.P.Inventors: Saeed S. Ghassemzadeh, Jason Vincent Bellorado, Ashley B. Tarokh
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Publication number: 20100304681Abstract: A technique for reducing interference between a direct-sequence ultra-wideband communications system and a narrowband communications system uses interference-rejecting spreading codes to reduce signal power in a frequency band associated with the narrowband communications system. A method of operating an ultra-wideband communications system includes applying an interference-rejecting spreading code to a signal for transmission. The interference-rejecting spreading code is configured to reduce power in a particular frequency band of a transmit or receive power spectral density associated with the ultra-wideband signal without substantially reducing power outside that particular frequency band of the transmit or receive power spectral density associated with the ultra-wideband signal.Type: ApplicationFiled: November 20, 2009Publication date: December 2, 2010Inventors: Saeed S. Ghassemzadeh, Jason Vincent Bellorado, Ashley B. Tarokh