Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include processing circuitry configured to control the clock and data recovery circuit. The processing circuitry and the clock and data recovery circuit may be formed on a single substrate.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.

Abstract: An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage that is approximately equal to the first voltage.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage that is approximately equal to the first voltage.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

Abstract: A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.

Abstract: Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.

Abstract: An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.

Abstract: An amplifier stage or circuit for providing cross-point adjustment. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit also includes a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node that is configured to adjust an amount of current provided to the first and second data signals to create a signal offset. The circuit further includes a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage configured to provide the signal offset at a third and fourth node of the second stage to adjust the cross-point of the first and second signals.

Abstract: An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.

Abstract: Embodiments disclosed herein relate to an amplifier stage or circuit for providing a signal boost. The circuit includes an emitter-follower pair and a cross coupled differential pair. The cross coupled differential pair provides a feedback signal that provides a boost to a signal output by the emitter follower pair. In some embodiments, a capacitor of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided. In other embodiments, a current source of the cross coupled differential pair may be adjustable in order to vary the amount of boosting provided.

Abstract: An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.

Abstract: An amplifier output stage for reducing Electromagnetic Interference (EMI) that includes an output node and an input node. A first transistor has a base terminal coupled to the input node and has a collector terminal coupled to the output node. A second transistor has a base terminal coupled to an emitter terminal of the first transistor and has a collector terminal coupled to the output node. A third transistor has a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and has an emitter terminal coupled to a current source and to an emitter terminal of the second transistor. A resistor has a first terminal coupled to a base terminal of the third transistor and has a second terminal coupled to the emitter terminal of the first transistor.

Abstract: An amplifier stage or circuit for providing cross-point adjustment. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit also includes a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node that is configured to adjust an amount of current provided to the first and second data signals to create a signal offset. The circuit further includes a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage configured to provide the signal offset at a third and fourth node of the second stage to adjust the cross-point of the first and second signals.