Patents by Inventor Jaspreet Singh Gambhir

Jaspreet Singh Gambhir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979232
    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 7, 2024
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Patent number: 11809363
    Abstract: A method for debugging an electronic subsystem is disclosed. The method includes converting a first message in a first protocol format received at a first functional logical block of a plurality of functional logical blocks of an electronic subsystem into a second message in a second protocol format at the first functional logical block, wherein the second message includes a unique identifier (UID), and generating a first trace file corresponding to the first functional logical block, wherein the first trace file includes the UID. The method includes forwarding the second message from the first functional logical block to a second functional logical block. The method includes generating a second trace file corresponding to the second functional logical block, wherein the second trace file includes the UID, and performing an analysis on the first and the second functional logical blocks.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: November 7, 2023
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Patent number: 11705986
    Abstract: A method and a system for correcting cyclic redundancy check (CRC) for a frame with last bytes changed are provided. The method includes acquiring a data frame, calculating a CRC of a modified data frame, and determining a corrected CRC for the data frame based on at least the CRC of the modified data frame and a CRC correction field calculated on the bytes to be replaced at the end of the frame. An altered data frame includes the data frame with a number of last bytes of the data frame replaced with new bytes.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: July 18, 2023
    Assignee: Synopsys, Inc.
    Inventors: Jishnu De, Jaspreet Singh Gambhir, Jitendra Puri
  • Publication number: 20230086197
    Abstract: A system performs verification of Ethernet hardware. A data frame including a first portion for storing a checksum value and a second portion for storing a timestamp value is received. The second portion of data frame is set to zero. A timestamp value for including in second portion of the data frame is received. A modified checksum value is determined based on the checksum value included in the first portion of the data frame and the timestamp value. A cyclic redundancy check (CRC) value is determined for the data frame by nullifying the checksum value in the data frame and considering the timestamp value. A final CRC value is determined by combining the CRC value for the data frame and a CRC correction value based on the checksum. The modified data frame is sent for processing using an emulator.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 23, 2023
    Inventors: Jishnu De, Jaspreet Singh Gambhir
  • Publication number: 20220209889
    Abstract: A method and a system for correcting cyclic redundancy check (CRC) for a frame with last bytes changed are provided. The method includes acquiring a data frame, calculating a CRC of a modified data frame, and determining a corrected CRC for the data frame based on at least the CRC of the modified data frame and a CRC correction field calculated on the bytes to be replaced at the end of the frame. An altered data frame includes the data frame with a number of last bytes of the data frame replaced with new bytes.
    Type: Application
    Filed: December 30, 2021
    Publication date: June 30, 2022
    Inventors: Jishnu DE, Jaspreet Singh GAMBHIR, Jitendra PURI
  • Patent number: 8248945
    Abstract: A method is provided for managing a transmit buffer using per priority pause flow control. An Ethernet transceiver generates packet descriptors identifying packets to be transmitted that are stored in memory. A priority is assigned to each descriptor and associated packet. Each descriptor is loaded into a queue having a queue priority associated with the descriptor priority. In response to accessing a first descriptor, output from a selected first priority queue, a first packet associated with the first descriptor is fetched into a transmit buffer from the memory. If subsequent to fetching the first packet, a per priority flow control message is received pausing first priority packets, the first packet is flushed from the transmit buffer. Then, a second descriptor is accessed from a selected second priority queue, and a second packet associated with the second descriptor is fetched and transmitted from the transmit buffer.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: August 21, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Satish Sathe, Satish Singh, Jaspreet Singh Gambhir, Sundeep Gupta