Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

Abstract: A chip package assembly having pillars extending between an interconnect layer and solder balls, and methods for manufacturing the same are provide. The pillars decouple stress from the interconnect layer, making crack initiation and propagation to the interconnect layer less likely, resulting in a more robust assembly. In one example, a chip package assembly is provided that includes an integrated circuit (IC) die, an interconnect layer and a plurality of pillars. The IC dies includes a die body containing functional circuitry. The body has a lower surface, an upper surface and sides. The IC die includes contact pads coupled to the functional circuitry and exposed on the lower surface of the die body. The interconnect layer is formed on the lower surface of the body. The plurality of pillars are formed on the interconnect layer and electrically couple to the contact pads through routing formed through the interconnect layer.

Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.

Abstract: An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

Abstract: A method of coordinating a plurality of radio access networks (RANs) includes aggregating, with a gateway, communications interfaces between a plurality of RANs and a packet core network through the gateway. A plurality of radio nodes (RNs) in each of the RANs is communicatively coupled to the gateway and to user equipment (UE) devices associated with the RNs in each of the RANs. The gateway also controls and coordinates mobility of the UE devices within and among the RANs. In addition, the gateway acts as a virtual enhanced NodeB (eNB) to the packet core network, thereby hiding the aggregated communications interfaces from the packet core network.

Abstract: A proactive data recovery system is provided. The system includes a memory having computer-readable instructions stored therein and a processor configured to execute the computer-readable instructions to access a data storage platform and to monitor a plurality of parameters indicative of a requirement of data restore and/or recovery for the data storage platform. The requirement corresponds to a predicted occurrence of a disaster event. The processor is further configured trigger backup of data stored in the data storage platform based upon the plurality of parameters to create a restore package and to initiate the data restore and/or data recovery operation for the data storage platform using the restore package in response to the occurrence of the disaster event.

Abstract: Aspects of the disclosure relate to a multipoint environment that enables a station (STA) to communicate with multiple access points (APs) and an AP to communicate with multiple STAs in a single wireless protocol stack. For example, a STA can authenticate simultaneously with multiple APs and decode any data packet that includes in a header a destination address that matches an address of the STA, irrespective of the source address included in the header of the data packet. Similarly, an AP can decode any data packet that includes in a header a destination address that matches an address of the AP or that matches a wildcard address associated with the AP, irrespective of the source address included in the header of the data packet.

Abstract: Aspects of the disclosure relate to a multipoint environment that enables a station (STA) to communicate with multiple access points (APs) and an AP to communicate with multiple STAs in a single wireless protocol stack. For example, a STA can authenticate simultaneously with multiple APs and decode any data packet that includes in a header a destination address that matches an address of the STA, irrespective of the source address included in the header of the data packet. Similarly, an AP can decode any data packet that includes in a header a source address that matches an address of an authenticated STA, irrespective of the destination address included in the header of the data packet.

Abstract: Structured data archival with reduced downtime is disclosed. One example is a system including a deployer that manages an active table (AT), and a non-active table (NAT), and creates an intermediate table (IT) to record, during data archival, changes to the data to be archived. The deployer creates triggers on the AT and the NAT to facilitate the record, by the IT, of the changes to the data to be archived. An archiver initiates the data archival by archiving the copy of the data to be archived from the NAT, merges the recorded data from the IT to the NAT upon receiving an indication that the client access to the AT is not enabled, and switches the client access from the AT to the NAT by changing a table synonym, where the client access to the NAT is enabled upon completion of the data archival.

Abstract: Provided herein is a personal care composition that can exhibit an increased vapor release while maintaining physical stability and texture. The personal care composition can have from about 35% to about 90% petrolatum, an additional microcrystalline wax having a needle penetration at 25° C. of from about 35 to about 75 dmm, from about 1% to about 8% of a gelling agent mixture, and from about 20% to about 50% of an olfactory composition, all by weight of the composition.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.

Abstract: Examples described herein provide techniques for multi-die device structures having improved gap uniformity between neighboring dies. In some examples, a first die and a second die are attached to an interposer. A first gap is defined by and between the first die and the second die. At least one of the first die or the second die is etched at the first gap. The etching defines a second gap defined by and between the first die and the second die. The first die, the second die, and the interposer are encapsulated with an encapsulant. The encapsulant is disposed in the second gap.

Abstract: A resource recommendation system is described to recommend and standardize resource tagging in a networked computing environment. In one example, cloud resources and related data are discovered, a database of the discovered information is generated, machine learning is applied to the database to build a prediction model, and tags for the resources are recommended, based on the prediction model, at a computing device.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die.

Abstract: A method of coordinating a plurality of radio access networks (RANs) includes aggregating, with a gateway, communications interfaces between a plurality of RANs and a packet core network through the gateway. A plurality of radio nodes (RNs) in each of the RANs is communicatively coupled to the gateway and to user equipment (UE) devices associated with the RNs in each of the RANs. The gateway also controls and coordinates mobility of the UE devices within and among the RANs. In addition, the gateway acts as a virtual enhanced NodeB (eNB) to the packet core network, thereby hiding the aggregated communications interfaces from the packet core network.

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Abstract: Systems and methods are disclosed that provide a closed loop power control system including adaptively adjusting the desired target SINR over time so as to ultimately achieve a feasible SINR. In one implementation, a method is provided of optimizing uplink closed loop power control in a RAN in which one or more base stations each service a plurality of mobile stations, including: determining a power level for each mobile station for its respective uplink transmissions, including measuring a current achieved SINR for each mobile station; and for each mobile station, adjusting the power level to be sufficiently high to meet desired transmission characteristics but not so high as to cause unnecessary interference with transmissions from other mobile stations, by adjusting a desired target SINR based on factors selected from the following: current and prior achieved SINRs, current and prior interference measurements, and current and prior transmission power control commands.