Abstract: An apparatus for reducing noise in fingerprint sensing circuits is disclosed in one embodiment of the invention as including a fingerprint sensing area onto which a user can apply a fingerprint. An analog front end is coupled to the fingerprint sensing area and is configured to generate an analog response signal. An analog-to-digital converter (ADC) samples the analog response signal and converts the sample to a digital value, which may be received by a digital device such as a processor or CPU. To reduce the amount of the noise that is present in the analog response signal and therefore reflected in the digital value, the digital device may be shut down while the ADC is sampling the analog response signal.

Abstract: A system and method is disclosed for minimizing power consumption of a sensor unit that is capable of detecting an object. Main circuitry operates the sensor unit in a high power mode of operation when the sensor unit detects an object. Low power control circuitry operates the sensor unit in a low power mode of operation when the sensor unit does not detect an object within a pre-determined period of time. The low power control circuitry also comprises a counter to periodically determine when to restore the sensor unit to a high power mode of operation. One advantageous embodiment of the sensor unit is a fingerprint sensor unit for detecting a finger to obtain fingerprint information.

Abstract: An integrated circuit (20) includes a low voltage inhibit (LVI) circuit (21) to protect an internal circuit (22) against losses in power supply voltage. The LVI circuit (21) includes primary (30) and secondary (35) LVI circuits. The primary LVI circuit (30) is a high-precision analog circuit which is selectively enabled when the secondary LVI circuit (35) senses that the power supply voltage is approaching a critical range. The primary LVI circuit (30) resets an internal circuit (22) of the integrated circuit (20) when it senses the power supply voltage falling below a critical level. Thus, the higher current primary LVI circuit (30) need only be enabled when a more precise power supply voltage measurement is required. The LVI circuit (21) also includes a disabling circuit (40) which latches an active output of the primary LVI circuit (30) and then disables the primary LVI circuit (30).

Abstract: A combined multiple memory array is disclosed which includes at least two differing types of memory arrays located next to and aligned to one another. The individual memory cells of the differing memory arrays are designed wherein the x pitches may vary in order to allow the y pitches to be substantially equal. A common set of row decoders provide common wordline decoding to the differing memory arrays. The memory arrays need not have the same number of words or bits to share the common row decoders. The column decoders may be separate for each array to account for different word sizes. A common set of column decoders is possible with equal word lengths from each array. A significant savings in silicon area may be saved by combining the multiple arrays.

Abstract: An operational amplifier is provided having a null offset that may be digitally adjusted quickly and accurately. The operational amplifier includes a cascode current mirror in an output stage wherein a small portion of current in the cascode current mirror is diverted away into a digitally controlled current divider. The more current that is diverted away, the larger the differential voltage that is created between the inverting and noninverting inputs of the operational amplifier. The current is increased until the output of the operational amplifier switches from the positive supply voltage to the ground supply voltage or vise versa. Additionally, a compensation capacitor at the output of the operational amplifier is switched out of the circuit during adjustment to speed up the null offset adjustment. Because the current being adjusted is not directly at the inputs of the operational amplifier the common mode input range is not deteriorated.

Abstract: A complementary voltage comparator is described wherein a CMOS operational amplifier having an input stage comprising N-channel field effect transistors is coupled with a CMOS operational amplifier having an input stage comprising P-channel field effect transistors. The outputs of the operational amplifiers are converted to currents and combined to indicate the relative magnitudes of the voltages being compared. This configuration allows the range of input voltages to vary over the full range of supply voltages and negates the need for offset correction.

Abstract: A system and method is disclosed for minimizing power consumption of a sensor unit that is capable of detecting an object. Main circuitry operates the sensor unit in a high power mode of operation when the sensor unit detects an object. Low power control circuitry operates the sensor unit in a low power mode of operation when the sensor unit does not detect an object within a pre-determined period of time. The low power control circuitry also comprises a counter to periodically determine when to restore the sensor unit to a high power mode of operation. One advantageous embodiment of the sensor unit is a fingerprint sensor unit for detecting a finger to obtain fingerprint information.