Patents by Inventor Jau Soon Chee

Jau Soon Chee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Metal layer independent version identifier
    Patent number: 10032723
    Abstract: Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status bit, gate circuitry, first selector circuitry in a first layer, and second selector circuitry in a second layer. The gate circuitry generates a value for the status bit based at least on a first input and a second input. The first selector circuitry is coupled to the gate circuitry and is configured to select a value for the first input. The second selector circuitry is coupled to the gate circuitry and is configured to select a value for the second input. The gate circuitry generates a default value for the status bit when the first input and the second input each have a default value and generates an opposite value for the status bit when either the first input or the second input has an opposite value.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Karthik Tammanur Ranganathan, Jau Soon Chee, Himanshu Kukreja
  • METAL LAYER INDEPENDENT VERSION IDENTIFIER
    Publication number: 20180151506
    Abstract: Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status bit, gate circuitry, first selector circuitry in a first layer, and second selector circuitry in a second layer. The gate circuitry generates a value for the status bit based at least on a first input and a second input. The first selector circuitry is coupled to the gate circuitry and is configured to select a value for the first input. The second selector circuitry is coupled to the gate circuitry and is configured to select a value for the second input. The gate circuitry generates a default value for the status bit when the first input and the second input each have a default value and generates an opposite value for the status bit when either the first input or the second input has an opposite value.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Inventors: Karthik Tammanur Ranganathan, Jau Soon Chee, Himanshu Kukreja