Patents by Inventor Javesh Vrajlal Sheth

Javesh Vrajlal Sheth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual bus network cache controller system having rapid invalidation cycles and reduced latency for cache access
    Patent number: 5845324
    Abstract: A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: December 1, 1998
    Assignee: Unisys Corporation
    Inventors: Theodore Curt White, Javesh Vrajlal Sheth