Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.

Abstract: An electronic device may include: a load and a voltage regulator coupled to the load and configured to provide a load current, where the voltage regulator includes a first and a second pass device coupled in parallel and configured to operate simultaneously. A method may include providing current to a load using a first and a second pass device coupled in parallel and configured to operate simultaneously, where the first device provides a first current corresponding to a high-frequency component and the second device provides a second current corresponding to a low-frequency component; in response to a decrease in a low-frequency component, causing the second current to decrease and causing the low-frequency component to increase; and in response to an increase in the low-frequency component, causing the second current to increase and causing the low-frequency component to decrease.

Abstract: A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the charge path than a second node of the charge path. The second node is coupled to an output of the sample and hold circuit to provide an output voltage. The sample and hold circuit includes a comparator circuit that compares the voltage of the first node and the voltage of the second node. When the comparator circuit determines that the voltage of the first node is a first condition with respect to a voltage of the second node, a voltage source provides a charging voltage on the first path to charge a first capacitor and a second capacitor to the charging voltage.

Abstract: An electronic device may include: a load and a voltage regulator coupled to the load and configured to provide a load current, where the voltage regulator includes a first and a second pass device coupled in parallel and configured to operate simultaneously. A method may include providing current to a load using a first and a second pass device coupled in parallel and configured to operate simultaneously, where the first device provides a first current corresponding to a high-frequency component and the second device provides a second current corresponding to a low-frequency component; in response to a decrease in a low-frequency component, causing the second current to decrease and causing the low-frequency component to increase; and in response to an increase in the low-frequency component, causing the second current to increase and causing the low-frequency component to decrease.

Abstract: A sample-and-hold circuit, which includes a hold capacitor at its output terminal and at least one intermediate capacitor, intermittently receives an input voltage, and a first value of a switch enable signal causes the sample-and-hold circuit to sample the input voltage and to charge the at least one intermediate capacitor and the hold capacitor to the input voltage, and when it is not receiving the input voltage, a second value of the switch enable signal causes the sample-and-hold circuit to hold, at its output terminal, the input voltage until the hold capacitor discharges, which starts to discharge only after the at least one intermediate capacitor has substantially discharged.

Abstract: In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.