Abstract: A quantum computing system including plural base configurations each configured including a first quantum bit group configured from first quantum bits arranged so as to form a single column without mutual coupling, a second quantum bit group configured from second quantum bits arranged so as to form a single column with adjacent ones of the second quantum bits coupled together and each of the second quantum bits coupled to the first quantum bit that is arranged in a same row, and a third quantum bit coupled to all of the second quantum bits. The plural base configurations are arranged so as to form a single column with the third quantum bits in adjacent ones of the base configurations coupled together. In a quantum computing circuit configuration, a two-dimensional cluster state or a three-dimensional cluster state is accordingly realized with two-dimensional control wiring, or surface code is accordingly realized with a pseudo two-dimensional superconducting circuit.

Abstract: A quantum computing system including plural base configurations each configured including a first quantum bit group configured from first quantum bits arranged so as to form a single column without mutual coupling, a second quantum bit group configured from second quantum bits arranged so as to form a single column with adjacent ones of the second quantum bits coupled together and each of the second quantum bits coupled to the first quantum bit that is arranged in a same row, and a third quantum bit coupled to all of the second quantum bits. The plural base configurations are arranged so as to form a single column with the third quantum bits in adjacent ones of the base configurations coupled together. In a quantum computing circuit configuration, a two-dimensional cluster state or a three-dimensional cluster state is accordingly realized with two-dimensional control wiring, or surface code is accordingly realized with a pseudo two-dimensional superconducting circuit.

Abstract: With a simple circuit configuration which does not conduct high frequency signal processing, a quantum computing device, a quantum bit readout processing unit of the quantum computing device, and a quantum bit readout processing method are provided. By controlling a quantum bit structure, which is formed with a counter electrode coupling with a quantum box electrode through a first tunnel barrier, with a gate voltage, a Cooper-pair extracted from the quantum box electrode after computation is accumulated in a trap electrode coupling with the quantum bit structure by sandwiching a second tunnel barrier. By coupling the trap electrode and an island electrode of a readout single electron transistor through a static capacitance, a change of electric charge in the trap electrode is read out as a direct current value of the single electron transistor.

Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.

Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.

Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.

Abstract: A control quantum bit circuit and a target quantum bit circuit each have a quantum box electrode including a superconductor, a counter electrode coupled to the quantum box electrode through a tunnel barrier, and a gate electrode coupled to the quantum box electrode through a gate capacitor. The quantum box electrode of the control quantum bit circuit is coupled to the quantum box electrode of the target quantum bit circuit through a box-electrode coupling capacitor.

Abstract: High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source 1 and a drain 2 to change a gate voltage, a current discretely flows between the source 1 and the drain 2 in accordance with quantized electrostatic energy levels in an island electrode 3. The switching ON/OFF of the current between the source 1 and the drain 2 in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer 6, its electric field is applied to the island electrode 3. The current between the source 1 and the drain 2 in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer 6, and stored data can be held even if power supply is cut off.

Abstract: In plural oscillation systems each of which can be described by the van der Pol equation, each oscillation system is reciprocally connected with at least one oscillation system other than the own oscillation system by a coupling factor to realize automatically the phenomenon of synchronization of the respective oscillation systems to enable spontaneous tuning of the entire system. A self-excited oscillation of an oscillation system prescribed by a van der Pol equation is controlled on/off by varying an applied voltage as a variable.