Abstract: Initial source shapes for source mask optimization are determined based on a layout of the lithographic mask. In one approach, a layout of a lithographic mask is received. Different sections of the lithographic mask, referred to as clips, are selected. These clips are applied to a machine learning model which infers source shapes from the clips. The inferred source shapes are used as the initial source shapes for source mask optimization.

Abstract: Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural network, can then be used to predict a set of failures for a given design intent. Next, for each predicted failure, a reticle enhancement technique (RET) recipe may be selected based on the failure mode of the failure, and the selected RET recipe may be applied to an area around the location of the failure.

Abstract: Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural network, can then be used to predict a set of failures for a given design intent. Next, for each predicted failure, a reticle enhancement technique (RET) recipe may be selected based on the failure mode of the failure, and the selected RET recipe may be applied to an area around the location of the failure.

Abstract: A system and method accurately translate a structural data file (30) that describes a complex logic circuit into a simulation model file (40) executable by a simulator (42). A net-list (34) is traversed, and the resulting model description is compiled into structural partitions including a WHEN-CONDITION partition (WC) that identify boundaries between synchronous and asynchronous subcircuits. The simulation model is also divided into execution time levels by a partitioned levelization method. Asynchronous feedback loops, which ordinarily lead to levelization failures, are correctly modeled by inserting time delay "levelers" (254, 262) into the feedback loop model. The resulting simulation model includes re-evaluation and evaluation stability checking steps (152, 230, 232, 276) that provide correct functional and timing evaluation of the simulation model.