Abstract: The invention is a multiple mode transmission system that interconnects the computer of a user with the Internet. The system has a first link that is a relatively low bandwidth telephone system. The system also has a second link that is a relatively high bandwidth television system. The television link can be either terrestrial or cable. The user would send an information request to the Internet across the telephone system. The actual information would be sent to the user via the television system. Scheduling data that informs the user of the time, channel, and exact location of the information in the television signal is sent to the user across the telephone system. The scheduling data is used by the inventive system to program the TV tuner that is used by the computer to receive the TV signal. The information can be encrypted, and the key would be included with the scheduling data. The channels can be dedicated data channels.

Abstract: A system and method for illuminating an area proximate a trailer, such as a boat or snowmobile trailer. At least one area illuminating light is connected to an area illuminating lighting control member. The area illuminating lighting control member receives and interprets trailer lighting control signals for determining when to activate and deactivate the area illuminating light. Control signals include is a trailer tow vehicle "lights on" condition combined with a second trailer lighting control signal, such as a "reverse lights on" indication, or indications from a water sensor or manual switch. The area illuminating lighting control member also receives a set of trailer lighting control signals for automatically deactivating the trailer illuminating lighting, including a "running light off" indication, a "brake lights on" indication, and/or a "turn signal lights on" indication.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) assocated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: Disclosed is an image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data.

Abstract: A prefabricated overhead building assembly and components making up this assembly are disclosed herein. The assembly includes a prefabricated overhead building structure, for example, a prefabricated roof, and a suspended ceiling system connected to and directly under the overhead structure. This ceiling system is comprised of a number of support runners and connectors which connect the support runners together to form a ceiling support grid supporting, for example, ceiling tile. The ceiling system also includes arrangements of cooperating components which fixedly connect the support grid to the overhead structure at alternative spaced positions below the overhead structure.