Patents by Inventor Jay C. Wells

Jay C. Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device and method for maximizing performance on a memory interface with a variable number of channels
    Patent number: 7523230
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 21, 2009
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
  • Device and method for maximizing performance on a memory interface with a variable number of channels
    Patent number: 6952745
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
  • Device and method for maximizing performance on a memory interface with a variable number of channels
    Patent number: 6766385
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
  • Device and method for maximizing performance on a memory interface with a variable number of channels
    Publication number: 20030131161
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 10, 2003
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert