Patents by Inventor Jay C. Yun

Jay C. Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9842562
    Abstract: A method, an apparatus, and a computer program product for modulating optics in a display are provided. An apparatus forms a plurality of zone plates in a liquid crystal using electric fields. Each zone plate has a center, and the centers are aligned along a first axis of the display. The apparatus moves the plurality of zone plates in a first direction along a second axis of the display different from the first axis of the display, while maintaining alignment of the centers of the plurality of zone plates along the first axis. Such movement is provided through repositioning of electric fields through the liquid crystal.
    Type: Grant
    Filed: January 13, 2013
    Date of Patent: December 12, 2017
  • Publication number: 20140198128
    Abstract: A method, an apparatus, and a computer program product for modulating optics in a display are provided. An apparatus forms a plurality of zone plates in a liquid crystal using electric fields. Each zone plate has a center, and the centers are aligned along a first axis of the display. The apparatus moves the plurality of zone plates in a first direction along a second axis of the display different from the first axis of the display, while maintaining alignment of the centers of the plurality of zone plates along the first axis. Such movement is provided through repositioning of electric fields through the liquid crystal.
    Type: Application
    Filed: January 13, 2013
    Publication date: July 17, 2014
  • Patent number: 8269775
    Abstract: This disclosure describes techniques for removing vertex points during two-dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: September 18, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Alexei V. Bourd, Guofang Jiao, Jay C. Yun
  • Patent number: 8203564
    Abstract: Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: June 19, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Guofang Jiao, Angus M. Dorbie, Yun Du, Chun Yu, Jay C. Yun
  • Publication number: 20080198168
    Abstract: Techniques for supporting both 2-D and 3-D graphics are described. A graphics processing unit (GPU) may perform 3-D graphics processing in accordance with a 3-D graphics pipeline to render 3-D images and may also perform 2-D graphics processing in accordance with a 2-D graphics pipeline to render 2-D images. Each stage of the 2-D graphics pipeline may be mapped to at least one stage of the 3-D graphics pipeline. For example, a clipping, masking and scissoring stage in 2-D graphics may be mapped to a depth test stage in 3-D graphics. Coverage values for pixels within paths in 2-D graphics may be determined using rasterization and depth test stages in 3-D graphics. A paint generation stage and an image interpolation stage in 2-D graphics may be mapped to a fragment shader stage in 3-D graphics. A blending stage in 2-D graphics may be mapped to a blending stage in 3-D graphics.
    Type: Application
    Filed: February 16, 2007
    Publication date: August 21, 2008
    Inventors: Guofang Jiao, Angus M. Dorbie, Yun Du, Chun Yu, Jay C. Yun