Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

Abstract: A temperature sensor includes a constant current source and a transistor stack connected to the constant current source. The transistor stack includes a first transistor having a base connected to the constant current source and a collector coupled to a supply voltage. The collector of the first transistor is electrically isolated from the base of the first transistor. The transistor stack includes a second transistor connected to the first transistor. The second transistor has a collector connected to an emitter of the first transistor and has a base connected to the collector of the second transistor. The transistor stack includes an output node disposed between the constant current source and the base of the first transistor. A voltage of the output node is indicative of a temperature.

Abstract: Methods for fabricating a semiconductor device are provided. In one embodiment, the method includes forming a Sub-Isolation Buried Layer (SIBL) stack over a semiconductor substrate. The SIBL stack includes a polish stop layer and a sacrificial implant block layer. The SIBL stack is patterned to create an opening therein, and the semiconductor substrate is etched through the opening to produce a trench in the semiconductor substrate. Ions are implanted into the semiconductor substrate at a predetermined energy level at which ion penetration through the patterned SIBL stack is substantially prevented to create a SIBL region beneath the trench. After ion implantation, a trench fill material is deposited over the SIBL stack and into the trench. The semiconductor device is polished to remove a portion of the trench fill material along with the sacrificial implant block layer and expose the polish stop layer.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

Abstract: A temperature sensor includes a constant current source and a transistor stack connected to the constant current source. The transistor stack includes a first transistor having a base connected to the constant current source and a collector coupled to a supply voltage. The collector of the first transistor is electrically isolated from the base of the first transistor. The transistor stack includes a second transistor connected to the first transistor. The second transistor has a collector connected to an emitter of the first transistor and has a base connected to the collector of the second transistor. The transistor stack includes an output node disposed between the constant current source and the base of the first transistor. A voltage of the output node is indicative of a temperature.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), intrinsic base (161, 163) and collector (190) are formed in a semiconductor body (115). An emitter contact (154) has a region (1541) that overlaps a portion (1293, 1293?) of an extrinsic base contact (129). A sidewall (1294) is formed in the extrinsic base contact (129) proximate a lateral edge (1543) of the overlap region (1541) of the emitter contact (154). The sidewall (1294) is amorphized during or after formation so that when the emitter contact (154) and the extrinsic base contact (129) are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall (1294) so that part (183) of the highly conductive silicided extrinsic base contact (182, 183) extends under the edge (1543) of the overlap region (1541) of the emitter contact (154) closer to the intrinsic base (161, 163), thereby reducing Rbx.

Abstract: A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first (251), second and third (252) openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100?) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44?, 44?). A dielectric ledge (453, 453?) is created during fabrication to separate the extrinsic base contract (46) from the collector (44, 44?, 44?) periphery (441). The dielectric ledge (453, 453?) underlies the transition region (461) where the extrinsic base contact (46) is coupled to the intrinsic base. (472) During device fabrication, a multi layer dielectric stack (45) is formed adjacent the intrinsic base (472) that allows the simultaneous creation of an undercut region (457, 457?) in which the intrinsic base (472) to extrinsic base contact (46) transition region (461) can be formed.

Abstract: High frequency performance of (e.g., silicon) bipolar devices (100, 100?) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), base (161) and collector (190) are formed in or on a semiconductor substrate (110). The emitter contact (154) has a portion (154?) that overhangs a portion (1293, 293?) of the extrinsic base contact (129), thereby forming a cave-like cavity (181, 181?) between the overhanging portion (154?) of the emitter contact (154) and the underlying regions (1293, 1293?) of the extrinsic base contact (129). When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity (181, 181?) so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact (154?) closer to the base (161, 163) itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first, second and third openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.