Patents by Inventor Jay T. Cantrell
Jay T. Cantrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6651126Abstract: A snapshot arbiter system for servicing multiple interrupt requests for a central processing unit (CPU) in a digital processor system, and for providing interrupts to the CPU corresponding to the interrupt requests. The system includes a synchronizer adapted to synchronize interrupt requests to a clock as they are received, and an interrupt masker adapted to receive a set of indicators identifying interrupt requests to be masked and to output active indicators that are a set of active interrupt request values corresponding to received interrupt requests that are not masked. Also included is a priority encoder block adapted to receive a set of priority values for respective interrupt requests and to provide as an output priority indicators that are a set of codes representing the priority values. A snapshot enable block is included, adapted to store enable indictors that are a set of bits representing currently enabled interrupt requests, and output those bits as enable bits.Type: GrantFiled: September 12, 2000Date of Patent: November 18, 2003Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Mark A. Granger, Ravishankar Kodavarti
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Patent number: 5694327Abstract: A digital circuit (11) for compelling storage of attributes and for providing output signals indicating status of the storage of attributes, the digital circuit comprising: a digital storage device (26); a first combinational logic circuit (20) connected to the digital storage device (26) for enabling the digital storage device (26) to store the attributes based upon a set of stable first compelled inputs and an enable signal; a second combinational logic circuit (18) connected to the digital storage device for clearing the digital storage device (26) based upon a set of stable second compelled inputs and a clear signal; a first logic gate (30) connected to the digital storage device (26) and the first combinational logic circuit (20) for outputting a signal representative of the attribute being stored in the digital storage device (26); and a second logic gate (28) connected to the digital storage device (26) and the second combinational logic circuit (18) for outputting a signal representative of the digitaType: GrantFiled: December 18, 1995Date of Patent: December 2, 1997Assignee: Texas Instruments IncorporatedInventors: Edward R. Schurig, Jay T. Cantrell
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Patent number: 5596749Abstract: A method of improving efficiency in computer systems through a novel arbitration scheme is disclosed. The arbitration scheme includes a bus arbiter circuit that transparently operates in both central arbitration and distributed arbitration computer systems. The bus arbiter circuit includes an arbitration request sequencer, an arbitration competition protocol sequencer, a multiplexer, a latch, two comparators, and a series of control status registers that together provide increased system efficiency by effectively self-preempting competition priorities on its own board, thus allowing tasks with the highest priorities to compete for mastership of the bus and eliminating priority inversions.Type: GrantFiled: September 21, 1992Date of Patent: January 21, 1997Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Edward R. Schurig
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Patent number: 5499344Abstract: An embodiment of the present invention is a digital circuit (block 12 of FIG.Type: GrantFiled: October 7, 1992Date of Patent: March 12, 1996Assignee: Texas Instruments IncorporatedInventors: Khodor S. Elnashar, Jay T. Cantrell, William Saperstein
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Patent number: 5452324Abstract: An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control circuit, a sample selector, and a sample circuit. The devices may be constructed on a single semiconductor substrate and may be connected to a bus structure having a microcomputer and a plurality of boards coupled to it. The delay locked loop circuit generates accurate delayed clock signals based on the reference clock. A positive edge synchronizer circuit, within the delay locked loop, serves as a programmable phase adjust for the sampling system. The positive edge synchronizer ensures proper phase relationship between the chosen delayed clock signal and the incoming data across semiconductor process variations. Packet enable circuit informs the delayed control circuit and the sample circuit when a start bit or stop bit is initiated in a data packet and enables those circuit blocks accordingly.Type: GrantFiled: September 23, 1992Date of Patent: September 19, 1995Assignee: Texas Instruments IncorporatedInventors: Clarence Lewis, Khodor Elnashar, Jay T. Cantrell
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Patent number: 5418825Abstract: A method and apparatus for a time domain boundary bridge circuit for capturing an event on an asynchronous input is described, comprising an S-R latch coupled to an asynchronous input, a first D flip-flop coupled to a synchronous clock and the output of the S-R latch, and a second D type flip-flop coupled to a synchronous clock and the output of the first D flip-flop, and having an output coupled to a circuit output terminal, operable to provide a synchronous output which reflects an event occurrence on the asynchronous input.Type: GrantFiled: March 28, 1994Date of Patent: May 23, 1995Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Edward R. Schurig
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Patent number: 5388225Abstract: A method and apparatus for a circuit physically realizing a time domain boundary buffer circuit for coupling an asynchronous sequential state machine controller to an asynchronous bus interface is described. A time domain boundary bridge latch circuit comprising a latch coupled to an asynchronous input, a delay element, and further coupled to a signal from the asynchronous sequential machine so that the signal from the asynchronous bus may be reliably captured is coupled to an input of the asynchronous sequential machine. The circuitry is designed to enable the asynchronous sequential machine to sample the asynchronous input as rapidly as possible without metastability errors. A second embodiment is disclosed for coupling an asynchronous sequential machine to a plurality of data bits on an asynchronous bus interface. Additional embodiments and applications are also disclosed.Type: GrantFiled: September 16, 1992Date of Patent: February 7, 1995Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Edward R. Schurig
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Patent number: 5387825Abstract: One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.Type: GrantFiled: August 20, 1992Date of Patent: February 7, 1995Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Edward R. Schurig
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Patent number: 5357613Abstract: A method and apparatus for a circuit physically realizing a time domain boundary buffer circuit for capturing data signals transmitted on an asynchronous domain bus and transmitting the data signals to a synchronous domain is described. The circuit comprises a data ready circuit and a data buffer circuit. The data ready circuit comprises a first flip flop is coupled to an asynchronous input, a second flip-flop is coupled to the synchronous domain clock and the output of the first flip flop, and a third flip-flop is coupled to the synchronous domain clock and the output of the second flip-flop, the circuit having an output coupled to a circuit output terminal; the third flip flop for providing a synchronous output which reflects an event occurrence on the asynchronous input. Other embodiments are also described.Type: GrantFiled: September 16, 1992Date of Patent: October 18, 1994Assignee: Texas Instruments IncorporatedInventors: Jay T. Cantrell, Edward R. Schurig
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Patent number: 5289060Abstract: A glitch filter identifies and eliminates positive edge and negative edge glitches without utilizing a high frequency sampling clock. The glitch filter comprises a programmable delay buffer string, two multiple input AND gates and a latch. The buffer string provides a plurality of incrementally delayed signals and utilizes them as signal samples thus simulating a high frequency sampling clock. The two multiple input AND gates serve to eliminate positive or negative edge glitches. The latch outputs the accurate filtered data without any positive or negative edge glitches.Type: GrantFiled: September 16, 1992Date of Patent: February 22, 1994Assignee: Texas Instruments IncorporatedInventors: Khodor S. Elnashar, Jay T. Cantrell, Clarence D. Lewis