Abstract: Embodiments of the present disclosure relate to a communication system for managing leased line networks. The system comprises of a router to route data from one network to another network, and a V.35 modem configured to receive the data from the router and transmit the data to a predefined destination using internet protocol (IP) network. The interface which connects the router with the V.35 modem is a V.35 interface. The IP network requires an ethernet interface to receive the data and to transmit the data to a destined location. The V.35 modem designed converts the V.35 interface to an ethernet interface, but since the ethernet interface is expensive, the V.35 modem converts the ethernet interface to an ADSL interface for establishing ADSL connection towards the IP network.

Abstract: Embodiments of the present disclosure relate to a communication system for managing leased line networks. The system comprises of a router to route data from one network to another network, and a V.35 modem configured to receive the data from the router and transmit the data to a predefined destination using internet protocol (IP) network. The interface which connects the router with the V.35 modem is a V.35 interface. The IP network requires an ethernet interface to receive the data and to transmit the data to a destined location. The V.35 modem designed converts the V.35 interface to an ethernet interface, but since the ethernet interface is expensive, the V.35 modem converts the ethernet interface to an ADSL interface for establishing ADSL connection towards the IP network. The system further comprising an interface to 3G/LTE/Wifi which is used as a redundant path in the event of failure of ADSL interface.

Abstract: An ATM switch having a plurality of input-ports and a plurality of output ports allowing a plurality of priority levels, which is highly modular allowing expansion of the number of cell buffers in a shared buffer pool, thus efficiently handling bursty traffic of one-to-one and one-to-many destination ports, using the bit slicing concept to reduce the operating speed of the switch, and decrease the cell buffer size requirement per slice along with reducing the number of shared queue memories per slice, aiding cost effective and efficient, very large scale integration (VLSI) implementation. It also allows configurability of input link speeds, taking care of the order of cell delivery to the output ports. The switch on receiving the input cell, searches for a free buffer in the shared pool, then routes the cell into this buffer and indexes the pointer into an output queue called the queue management module which uses a shared pool of queue memories.