Patents by Inventor Jayasanker Jayabalan

Jayasanker Jayabalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compliant probes and test methodology for fine pitch wafer level devices and interconnects
    Publication number: 20070040565
    Abstract: A compliant interposer sheet probe card and a method for testing a wafer or a wafer level package using the probe card are described. Test electronic circuits are connected on one side of a multi-layer substrate. A top side of a compliant interposer sheet is connected to an opposite side of the multi-layer substrate. A wafer or a wafer level package to be tested is contacted with pins on a bottom side of the compliant interposer sheet whereby the wafer or wafer level package can be tested.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 22, 2007
    Inventors: Jayasanker Jayabalan, Mihai Rotaru, Mahadevan Iyer, Andrew Ong