Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.

Abstract: Embodiments of the present disclosure generally include methods of specially programming a set of memory cells, wherein each specially programmed memory cell is specially programmed along with programming a plurality of wordlines, and wherein each memory cell is specially programmed by altering a bitline and gate voltage applied to the memory cell. The methods further includes performing a sensing operation across a set of strings in the array of memory cells, determining, based on the sensing operation, whether one or more strings failed to conduct during a sensing operation, and determining the last programmed wordline using the one or more strings that failed to conduct.

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Abstract: Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Abstract: A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.

Abstract: A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

Abstract: A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.

Abstract: A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

Abstract: Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.

Abstract: Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode, data is not written to memory cells in a sub-block that contains SGS transistors whose Vt does not meet the criterion. Hence, the possibility of data loss due to defective SGS transistors is avoided. However, in the sub-block mode, data is written to memory cells in a sub-block that does not contain SGS transistors whose Vt does not meet the criterion. Hence, data capacity is preserved.

Abstract: A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Abstract: A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.

Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.

Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.

Abstract: A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.

Abstract: A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.