Abstract: An interbus interface module enables storage and transfer of commands, messages and data between parallel a dual system bus operating on a first protocol and a subrequestor bus operating on a second protocol. The interface module serves a first group of requestors, such as multiple processors and main memory, for handling data transfers to and from the subrequestor bus via said dual system buses while also handling data transfers to and from a second group of requestors connected to the subrequestor bus.

Abstract: A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

Abstract: An Input/Output Module (IOM) interfacing multiple computers attached to a dual system bus. The IOM provides an interbus module which interfaces the dual system bus to a sub-requestor bus connecting multiple sub-requestor modules. The sub-requestor modules control a plurality of interface adaptors permitting data transfers to/from a variety of peripherals using different data protocols and clock rates. The requirements for the main host processors and memories in a computer system would be unduly burdensome were it not for the relief from these overhead operations by the input/output module which provides the tailoring of data transfer capability to and from a multiplicity of peripherals having many different types of protocols and clock rates.

Abstract: An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.

Abstract: A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

Abstract: A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

Abstract: A peripheral-controller (called a Data Link Processor) optimizes the rate of data transfers between a host computer and magnetic tape peripherals by use of a block counter sensing system for monitoring the occupation-status of word-blocks in a buffer memory. The peripheral-controller provides Automatic Read/Write Logic for buffer-peripheral tape transfers and a burst mode routine for rapid host-buffer transfers of data words. The sensing system provides means to inform a microcode sequencer when certain action routines should be executed in order to maintain steady error-free data transfer operations which minimize the need for retries of data transfer cycles previously initiated.

Abstract: A peripheral-controller is used to manage data transfers between peripheral units of the magnetic tape type. A program sequencer in the peripheral-controller can signal an automatic read-write selection logic and control unit to operate in the "automatic read" mode whereby an automatic read-logic unit will transfer data out of the magnetic tape peripheral unit into a buffer memory of the peripheral-controller on a continuous basis without further instructions being required from the program sequencer.

Abstract: A block counter sensing system for monitoring the occupation-status of word-blocks in a buffer memory of a peripheral-controller having Automatic Read/Write Logic for buffer-peripheral tape transfers and a burst mode routine for rapid host-buffer transfers of data words. The sensing system provides means to inform a microcode sequencer when certain action routines should be executed in order to maintain steady error-free data transfer operations which minimize the need for retries of data transfer cycles previously initiated.

Abstract: A data transfer system for transferring data from magnetic tape peripheral units to a peripheral-controller for temporary storage and subsequent transfer to a host computer. A tape control unit, connected to the magnetic tape peripheral units, provides clock signals to a synchronization logic circuit which controls the transfer of data through two sequential latching registers to a buffer memory in the peripheral-controller. The two sequential latching registers function as a buffering delay element together with an automatic read logic unit which allows the read logic unit to use a lesser number of cycle-steal times than would ordinarily be required, while still controlling a steady uninterrupted flow of data words.

Abstract: A peripheral-controller (designated as a data-link-processor) manages data transfers between a main host computer and a magnetic tape peripheral unit. The peripheral-controller uses a common front end providing an instruction sequencing unit and a buffer memory to store data-in-transit in six blocks of 256 words each. A peripheral-dependent circuit unit of the peripheral-controller can provide automatic read or automatic write data transfers between the buffer memory and the magnetic tape peripheral unit without further attention from said instruction sequencing unit.

Abstract: A data transfer system whereby a peripheral-controller manages data transfers between the host computer and a magnetic tape peripheral unit. Data undergoing transit, is temporarily stored in a buffer memory of the peripheral-controller and is monitored by a block counter monitoring system which informs a program-sequencer in the common control circuit unit of the peripheral-controller when data may be shifted into or out of the buffer memory in order to avoid or reduce the probability of access error conditions.

Abstract: A peripheral-controller is used to manage data transfers between magnetic tape peripheral units and a main host computer. A program sequencer in the peripheral-controller can initiate an automatic read-write selection logic and control unit to operate in the "automatic write" mode whereby an automatic write-logic unit will transfer data out of a buffer memory in the peripheral-controller and into a magnetic tape control unit on a continuous basis without further instructions being required from the program sequencer.