Patents by Inventor Jayne L. Mershon
Jayne L. Mershon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7630601Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.Type: GrantFiled: February 26, 2008Date of Patent: December 8, 2009Assignee: Intel CorporationInventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
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Publication number: 20080159689Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.Type: ApplicationFiled: February 26, 2008Publication date: July 3, 2008Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
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Patent number: 7373068Abstract: The invention provides an optical connection between a component on a printed circuit board (“PUB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.Type: GrantFiled: August 29, 2006Date of Patent: May 13, 2008Assignee: Intel CorporationInventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long, Michael W. Beckman
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Patent number: 7361842Abstract: A method, apparatus, and system for a printed circuit board (PCB) and package with an embedded air dielectric includes a conductor formed on a surface of a first core layer, a conductor layer overlaying an inner surface of a cavity formed in a second core layer, the conductor layer opposing the conductor, and a sealed air channel between and separating the conductor and the conductor layer from contacting each other. A gas in the sealed air channel provides a primary dielectric therein. The gas may be air.Type: GrantFiled: June 30, 2005Date of Patent: April 22, 2008Assignee: Intel CorporationInventors: Gary A. Brist, William O. Alger, Gary B. Long, Jayne L. Mershon, Michael W. Beckman
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Patent number: 7334325Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.Type: GrantFiled: November 16, 2004Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
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Patent number: 7282647Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.Type: GrantFiled: December 23, 2002Date of Patent: October 16, 2007Assignee: Intel CorporationInventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
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Patent number: 7234947Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.Type: GrantFiled: July 21, 2006Date of Patent: June 26, 2007Assignee: Intel CorporationInventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
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Patent number: 7121841Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.Type: GrantFiled: November 10, 2004Date of Patent: October 17, 2006Assignee: Intel CorporationInventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
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Patent number: 7036217Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.Type: GrantFiled: January 21, 2003Date of Patent: May 2, 2006Assignee: Intel CorporationInventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
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Publication number: 20040118597Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Applicant: Intel CorporationInventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
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Publication number: 20030101585Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.Type: ApplicationFiled: January 21, 2003Publication date: June 5, 2003Applicant: Intel CorporationInventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
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Patent number: 6509530Abstract: To mount electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are described.Type: GrantFiled: June 22, 2001Date of Patent: January 21, 2003Assignee: Intel CorporationInventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
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Publication number: 20020195269Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.Type: ApplicationFiled: June 22, 2001Publication date: December 26, 2002Applicant: Intel CorporationInventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon