Patents by Inventor Jayne L. Mershon

Jayne L. Mershon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7630601
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 8, 2009
    Assignee: Intel Corporation
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
  • Publication number: 20080159689
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PCB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Application
    Filed: February 26, 2008
    Publication date: July 3, 2008
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long
  • Patent number: 7373068
    Abstract: The invention provides an optical connection between a component on a printed circuit board (“PUB”) and an optical fiber embedded in the PCB. By optically connecting the component with the optical fiber, the component may use the optical fiber for high speed optical data communication.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Jayne L. Mershon, William O. Alger, Gary A. Brist, Gary B. Long, Michael W. Beckman
  • Patent number: 7361842
    Abstract: A method, apparatus, and system for a printed circuit board (PCB) and package with an embedded air dielectric includes a conductor formed on a surface of a first core layer, a conductor layer overlaying an inner surface of a cavity formed in a second core layer, the conductor layer opposing the conductor, and a sealed air channel between and separating the conductor and the conductor layer from contacting each other. A gas in the sealed air channel provides a primary dielectric therein. The gas may be air.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, William O. Alger, Gary B. Long, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7334325
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Patent number: 7282647
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Patent number: 7234947
    Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7121841
    Abstract: A compressible domed contact used as a portion of socket contact within an electrical socket to eliminate co-planarity issues and to achieve an effective electrical connection between the electrical socket and a microelectronic device. The compressible domed contact may be made of resilient material such that it will substantially return to its original shape after being compressed.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: William O. Alger, Gary B. Long, Gary A. Brist, Jayne L. Mershon, Michael W. Beckman
  • Patent number: 7036217
    Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: May 2, 2006
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
  • Publication number: 20040118597
    Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Applicant: Intel Corporation
    Inventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
  • Publication number: 20030101585
    Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.
    Type: Application
    Filed: January 21, 2003
    Publication date: June 5, 2003
    Applicant: Intel Corporation
    Inventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
  • Patent number: 6509530
    Abstract: To mount electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are described.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: January 21, 2003
    Assignee: Intel Corporation
    Inventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon
  • Publication number: 20020195269
    Abstract: According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Applicant: Intel Corporation
    Inventors: Tom E. Pearson, Carolyn R. McCormick, Jayne L. Mershon