Abstract: A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.

Abstract: A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift register and right shift and left shift control signals. Dependent on the input signals, the input circuit portion drives an input node coupled to the latching circuit portion with a data value to be shifted which corresponds to data from one of the previous and next single-latch circuits.

Abstract: A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop circuitry which is designed so as to significantly reduce the locking period associated with achieving the lock state of the delay lock loop. The delay lock loop circuit includes a first adjustable delay unit circuit for delaying the external clock so as to provide the DDR operation and includes a feedback loop having a shift register controlled by a phase detector which is used to set an optimum delay value. The delay value is then used to control the first delay unit circuit and determine the amount of delay time it provides.

Abstract: A sense amplifier having an ingegrated latch with level shift is disclosed, in which a pair of cross-connected inverters are connected between the outputs of the sense amplifier to provide a single stage amplifier. The sense amplifier performs level shift, sense amplifier and latching functions within a single circuit, thus reducing layout area and simplifying chip design while at the same time providing full swing complementary outputs. In addition, the sense amplifier is turned on for only a portion of the cycle to enable the data to be latched, with virtually no constant current comsumption in the circuit for holding the data, thereby reducing power consumption. Alternative embodiments are disclosed using conventional and tri-state latches.