Abstract: A digital-to-analog converter (DAC) for generating an output voltage according to an input code includes a first-type and a second-type sub-DAC's connected in series. The first-type sub-DAC includes a first resistor string and plural first switches, and receives a reference current to determine a first voltage drop. The first switches are controlled by a first portion of the input code to determine a voltage division of the first voltage drop. The second-type sub-DAC includes a second resistor string and plural second switches. The second switches are controlled by a second portion of the input code to determine a portion of the second resistor string to receive the reference current, wherein the portion of the second resistor string and the reference current determines a second voltage drop. The output voltage includes a sum of the second voltage drop and the voltage division of the first voltage drop.

Abstract: A power conversion circuit includes a first and a second power converters for generating a first and a second driving voltages respectively. The second power converter is a switching converter. In a short-circuit detection mode, the first driving voltage is regulated to the first driving level, and the second power converter is configured to operate in a pulse frequency modulation mode to regulate the second driving voltage to a short-circuit detection level, and when a switching frequency of the second power converter exceeds a threshold frequency, a short-circuit condition between the second driving voltage and the first driving voltage is determined.

Abstract: A power conversion circuit includes a first and a second power converters for generating a first and a second driving voltages respectively. The second power converter is a switching converter. In a short-circuit detection mode, the first driving voltage is regulated to the first driving level, and the second power converter is configured to operate in a pulse frequency modulation mode to regulate the second driving voltage to a short-circuit detection level, and when a switching frequency of the second power converter exceeds a threshold frequency, a short-circuit condition between the second driving voltage and the first driving voltage is determined.

Abstract: A display apparatus may be provided that includes a plurality of pixels; a plurality of pixel memories which drive a corresponding pixel in accordance with a column signal when a scanning line selection signal and an enable signal are both selected; and a controller which generates the scanning line selection signal, the enable signal, and the column signal such that each of the pixels is driven in a turn-on time occupation ratio corresponding to a data value for each of the pixels, and then applies the signals to a corresponding pixel memory. According to the embodiment, in a display apparatus which requires high resolution, high frame rate per pixel, and high gray scale representation capability, the change of the signal which is applied to the pixel for each time slot is relatively reduced, so that consumption of power for driving the pixel can be reduced.

Abstract: A digital sigma-delta modulator may be provided that includes: a multiplexer which receives N-bit input data from each of M number of input terminals and sequentially outputs; an adder which outputs carry out (CO) data and N-bit added data obtained by adding the N-bit input data and N-bit added data output in a previous cycle; a memory which divides the N-bit added data output from the adder into A-bit added data and (N?A)-bit added data and stores the A-bit added data and the (N?A)-bit added data; and a demultiplexer which receives the output carry out (CO) data and outputs to each of M number of output terminals.

Abstract: A display apparatus may be provided that includes a plurality of pixels; a plurality of pixel memories which drive a corresponding pixel in accordance with a column signal when a scanning line selection signal and an enable signal are both selected; and a controller which generates the scanning line selection signal, the enable signal, and the column signal such that each of the pixels is driven in a turn-on time occupation ratio corresponding to a data value for each of the pixels, and then applies the signals to a corresponding pixel memory. According to the embodiment, in a display apparatus which requires high resolution, high frame rate per pixel, and high gray scale representation capability, the change of the signal which is applied to the pixel for each time slot is relatively reduced, so that consumption of power for driving the pixel can be reduced.

Abstract: A digital sigma-delta modulator may be provided that includes: a multiplexer which receives N-bit input data from each of M number of input terminals and sequentially outputs; an adder which outputs carry out (CO) data and N-bit added data obtained by adding the N-bit input data and N-bit added data output in a previous cycle; a memory which divides the N-bit added data output from the adder into A-bit added data and (N?A)-bit added data and stores the A-bit added data and the (N?A)-bit added data; and a demultiplexer which receives the output carry out (CO) data and outputs to each of M number of output terminals.

Abstract: A frequency fine tuning circuit for use in a voltage-controlled oscillator is provided. The frequency tuning circuit includes a first varactor, a second varactor and a center bias unit. The second varactor is coupled to the first varactor at a first node. The center bias unit maintains a node voltage of the first node at a constant bias voltage level.

Abstract: A capacitor bank includes a first node, a second node, first blocking capacitors, N first AMOS varactors, second blocking capacitors and N second AMOS varactors. The first blocking capacitors have first terminals connected to the first node and second terminals where a bias voltage is applied. The N first AMOS varactors have first terminals connected to the second terminals of the first block capacitors. The second blocking capacitors have first terminals connected to the second node and second terminals where the bias voltage is applied. The N second AMOS varactors have first terminals connected to the second terminals of the second blocking capacitors and second terminals connected to second terminals of the first AMOS varactors, respectively, wherein N binary coded signals are applied to the respective second terminals of the first AMOS varactors and the second AMOS varactors. Therefore, phase-noise degradation caused by the FM modulation may be avoided.

Abstract: A frequency fine tuning circuit for use in a voltage-controlled oscillator is provided. The frequency tuning circuit includes a first varactor, a second varactor and a center bias unit. The second varactor is coupled to the first varactor at a first node. The center bias unit maintains a node voltage of the first node at a constant bias voltage level.

Abstract: Provided is a quadrature voltage controlled oscillator capable of varying a phase difference between an in-phase output signal and a quadrature output signal. The quadrature voltage controlled oscillator comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The first voltage controlled oscillator generates a first output and a second output. The second voltage controlled oscillator generates a third output and a fourth output. The first output is a positive in-phase signal, and the second output is a negative in-phase signal. The third output is a positive quadrature signal, and the fourth output is a negative quadrature signal. The first amplifier is controlled by a first current and drives the first output and the second output in response to the third output and the fourth output.

Abstract: A capacitor bank includes a first node, a second node, first blocking capacitors, N first AMOS varactors, second blocking capacitors and N second AMOS varactors. The first blocking capacitors have first terminals connected to the first node and second terminals where a bias voltage is applied. The N first AMOS varactors have first terminals connected to the second terminals of the first block capacitors. The second blocking capacitors have first terminals connected to the second node and second terminals where the bias voltage is applied. The N second AMOS varactors have first terminals connected to the second terminals of the second blocking capacitors and second terminals connected to second terminals of the first AMOS varactors, respectively, wherein N binary coded signals are applied to the respective second terminals of the first AMOS varactors and the second AMOS varactors. Therefore, phase-noise degradation caused by the FM modulation may be avoided.

Abstract: Provided is a quadrature voltage controlled oscillator capable of varying a phase difference between an in-phase output signal and a quadrature output signal. The quadrature voltage controlled oscillator comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The first voltage controlled oscillator generates a first output and a second output. The second voltage controlled oscillator generates a third output and a fourth output. The first output is a positive in-phase signal, and the second output is a negative in-phase signal. The third output is a positive quadrature signal, and the fourth output is a negative quadrature signal. The first amplifier is controlled by a first current and drives the first output and the second output in response to the third output and the fourth output.

Abstract: Voltage controlled oscillators include an amplifier that generates an oscillation output signal having an oscillation frequency based on an applied inductance and capacitance. An inductor coupled to the amplifier applies the inductance. A switched capacitor circuit includes a plurality of switches and capacitors selectably coupled to the amplifier through respective ones of the switches. A switched varactor circuit includes a plurality of switches and varactors selectably coupled to the amplifier through respective ones of the switches. The capacitances of the varactors are responsive to an applied control voltage. A control circuit is configured to select ones of the switches of the capacitor circuit and of the varactor circuit and to provide a selected control voltage to the varactor circuit to apply a desired capacitance to the amplifier.