Patents by Inventor Jea-Hee Kim
Jea-Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240151361Abstract: A hydrogen supply method includes a two-side heat exchange mode in which both introducing a second fluid into a hydrogen storage part after the second fluid exchanges heat with a first fluid in a second heat exchanger in a state in which a compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in a thermal device are performed. The method also includes a one-side heat exchange mode in which one of introducing the second fluid into the hydrogen storage part after the second fluid exchanges heat with the first fluid in the second heat exchanger in a state in which the compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in the thermal device is performed.Type: ApplicationFiled: August 30, 2023Publication date: May 9, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATIONInventors: Yeon Ho Kim, Hoon Mo Park, Kyung Moon Lee, Dong Hoon Nam, Ji Hye Park, Young Jin Cho, Jea Wan Kim, Byeong Soo Shin, Ji Hoon Lee, Ho Young Jeong, Suk Hoon Hong, Man Hee Park, Yeong Jun Kim, Jae Yeon Kim, Ho Chan An
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Patent number: 11955281Abstract: An electronic component includes: a multilayer capacitor including a capacitor body and a pair of external electrodes, respectively disposed on external surfaces of the capacitor body in a first direction; and an interposer disposed below the multilayer capacitor and including an interposer body, a pair of via holes penetrating through the interposer body, and a pair of via electrodes, respectively disposed in the via holes to be connected to the pair of external electrodes, respectively. 0.24T?t?0.3T, where “T” is a maximum height of the multilayer capacitor and “t” is a maximum height of the interposer.Type: GrantFiled: May 17, 2021Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jae Hoon Kim, Chang Hee Lee, Jea Hoon Lee, Hye Jin Kim, Yeo Ju Cho
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Patent number: 7867834Abstract: A manufacturing method of a semiconductor device according to an embodiment includes: forming a trench for a device isolation area and a semiconductor projection with a first width by etching a semiconductor substrate; forming an oxide film on the trench and the semiconductor projections; forming an insulating layer on the oxide film; exposing the upper surface of the semiconductor projection by polishing the insulating layer and the oxide film; forming a gate insulating layer at a lower region of the semiconductor projection; and etching the insulating layer and the oxide film on the substrate.Type: GrantFiled: July 18, 2007Date of Patent: January 11, 2011Assignee: Dongbu Hitek Co., Ltd.Inventors: Eun Soo Jeong, Jea Hee Kim
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Patent number: 7851317Abstract: A drift of a high voltage transistor formed using an STI (shallow trench isolation).Type: GrantFiled: May 22, 2008Date of Patent: December 14, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Jea-Hee Kim
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Patent number: 7829413Abstract: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device includes a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.Type: GrantFiled: June 27, 2008Date of Patent: November 9, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Jea Hee Kim
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Patent number: 7598110Abstract: A method for manufacturing a CMOS image sensor may include at least one of the following steps: Forming a salicide blocking layer on an entire surface of a semiconductor substrate having a photodiode area and a transistor. Forming a photoresist pattern inclined at an angle less 90° (e.g. between approximately 70° and approximately 80°) on and/or over a non-salicide area. Performing wet-etching on the salicide blocking layer using the photoresist pattern as an etching mask. Forming salicide on the salicide area after removing the photoresist pattern.Type: GrantFiled: August 24, 2007Date of Patent: October 6, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Jea-Hee Kim
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Patent number: 7588978Abstract: Embodiments relate to a method for forming a semiconductor device in which a first oxide layer may be deposited over a surface of a semiconductor substrate including high-voltage (HV) and low-voltage (LV) wells, the first oxide layer having a predetermined thickness corresponding to a high-voltage (HV) area of the well. A first photoresist pattern may be formed over a surface of the first oxide layer. An etching process may be performed using the first photoresist pattern as a mask, so that the first oxide layer is selectively etched until the semiconductor substrate is partially exposed, to form a first oxide layer pattern. A second oxide layer may be deposited over a surface of the semiconductor substrate including the first oxide layer pattern using the first photoresist pattern as a mask, the second oxide layer having a predetermined thickness corresponding to a low-voltage (LV) area of the well. The first photoresist pattern may be removed.Type: GrantFiled: August 29, 2007Date of Patent: September 15, 2009Assignee: Dongbu HiTek, Co., Ltd.Inventor: Jea-Hee Kim
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Patent number: 7566612Abstract: A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming, using an oxidation rate differential, an uneven structure in correspondence with a grain boundary of the metal layer; forming a dielectric layer on the lower electrode having the uneven structure; and forming an upper electrode on the dielectric layer.Type: GrantFiled: June 10, 2005Date of Patent: July 28, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea Hee Kim
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Patent number: 7560369Abstract: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the semiconductor substrate after forming the via hole, dry cleaning the semiconductor substrate after the wet cleaning, and forming a second metal line that is electrically connected with the first metal line through the via hole.Type: GrantFiled: June 21, 2006Date of Patent: July 14, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea-Hee Kim
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Publication number: 20090170303Abstract: Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device comprising a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.Type: ApplicationFiled: June 27, 2008Publication date: July 2, 2009Applicant: DONGBU HITEK CO., LTD.Inventor: Jea Hee Kim
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Publication number: 20090152661Abstract: A method for manufacturing the image sensor includes: forming a photoresist layer on a surface of an image sensor; exposing and developing the photoresist layer using a mask used for fabricating a plurality of micro-lenses, which has a number of first light shielding patterns aligned apart from one another and a number of second light shielding patterns, each being formed at a part, on which four adjacent edges of the first light shielding patterns are centered, so that a photoresist pattern is formed; and reflowing the photoresist pattern to fabricate a plurality of micro-lenses and a concave lens at each part, on which four adjacent edges of the micro-lenses are centered.Type: ApplicationFiled: December 9, 2008Publication date: June 18, 2009Inventor: Jea-Hee Kim
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Patent number: 7538393Abstract: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.Type: GrantFiled: November 5, 2007Date of Patent: May 26, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea-Hee Kim
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Publication number: 20090121282Abstract: An increase of charge storing capacity, prevention of an over-erase, and a reduction of ?Vth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.Type: ApplicationFiled: January 15, 2009Publication date: May 14, 2009Inventor: Jea-Hee KIM
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Patent number: 7498227Abstract: An increase of charge storing capacity, prevention of an over-erase, and a reduction of ?Vth may be achieved when a 2-bit/cell non-volatile memory device includes a gate of a predetermined width above a semiconductor substrate, an insulating layer between the gate and the semiconductor substrate and at lateral sides of the gate, having a greater width than the gate, a pair of storage layers at the lateral sides of the gate, a pair of blocking layers at the lateral sides of the gate and covering the pair of storage layers, a source and a drain formed in the semiconductor substrate at first opposed locations external to the gate, and a trap impurity implanted into the insulating layer at second locations external to the gate.Type: GrantFiled: August 16, 2005Date of Patent: March 3, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea-Hee Kim
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Publication number: 20080296678Abstract: A drift of a high voltage transistor formed using an STI (shallow trench isolation).Type: ApplicationFiled: May 22, 2008Publication date: December 4, 2008Inventor: Jea-Hee Kim
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Publication number: 20080286920Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a negative photoresist layer on a semiconductor substrate, forming a photoresist pattern on the negative photoresist layer, forming a well region in the semiconductor substrate, implanting ions into the semiconductor substrate, using the photoresist pattern as a mask, such that the ions are implanted into the well region, removing the photoresist pattern, and forming a gate region and a source/drain region on the semiconductor substrate.Type: ApplicationFiled: May 16, 2008Publication date: November 20, 2008Inventor: Jea Hee KIM
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Patent number: 7419899Abstract: A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the first region has a first width from an edge of the wafer. The trench pattern is formed above the wafer except for above the first region. The metal interconnection layer is formed above the wafer where the laser marking and the trench pattern are formed. The predetermined portion of the metal interconnection layer is removed, and the predetermined portion has a second width from the edge of the wafer equal to or greater than the first width. And the metal interconnection layer above the wafer where the trench pattern is formed is planarized to a predetermined thickness.Type: GrantFiled: May 30, 2006Date of Patent: September 2, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea Hee Kim
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Patent number: 7393778Abstract: A semiconductor device and a method for fabricating the same in which a protective oxide layer is formed on an insulating interlayer gap are disclosed. An example semiconductor device includes a semiconductor substrate having lower structures, an insulating interlayer on the semiconductor substrate to cover the lower structures, and an SiH4-oxide layer on the insulating interlayer. The SiH4-oxide has hydrogen constituents removed by displacement to prevent an amorphous material layer from being formed on the insulating interlayer. The example semiconductor device includes a contact hole in the insulating interlayer and the SiH4-oxide layer for exposing predetermined portions of the lower structures. Additionally, the example semiconductor device includes a contact plug formed inside the contact hole to electrically connect the lower structures with a metal line.Type: GrantFiled: December 28, 2004Date of Patent: July 1, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Jea Hee Kim
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Publication number: 20080149973Abstract: A method for manufacturing a semiconductor device is provided. The method includes: forming a gate insulating layer on a semiconductor substrate having an isolation layer formed therein, forming a gate electrode on the gate insulating, implanting low-concentration impurity ions on the semiconductor substrate at a first side of the gate electrode to form a lightly doped drain (LDD) region, forming a low-concentration impurity region on the semiconductor substrate at a second side of the gate electrode, implanting impurities into the low-concentration impurity region to form a photodiode, and forming micro pits on a top surface of the photodiode using a wet etching process.Type: ApplicationFiled: December 20, 2007Publication date: June 26, 2008Inventor: Jea Hee Kim
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Publication number: 20080142903Abstract: A semiconductor device and a method for manufacturing the same is disclosed, in which a spacer containing nitrogen therein has a tensile stress and enables device reliability improvement by improving the On-current without regard to the kind of transistor. The semiconductor device includes a semiconductor substrate; a gate insulating layer and a gate electrode on the semiconductor substrate; spacers at sidewalls of the gate electrode, wherein the spacer contains nitrogen to obtain or increase its tensile stress; and source and drain regions in the semiconductor substrate adjacent to the gate electrode.Type: ApplicationFiled: February 21, 2008Publication date: June 19, 2008Inventor: Jea Hee Kim