Abstract: Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed.

Abstract: Embodiments provide input/output devices having programmable logic that is programmable to operate input/output devices in one of two drive modes. In various embodiments, to operate an input/output device in a first drive mode, logic circuitry is programmable to couple a reference voltage to a gate of a transistor element of an output driver. In various embodiments, to operate an input/output device in a second drive mode, the logic circuitry is programmable to couple a bias voltage to the gate of the transistor element of the output driver. In various embodiments, the logic circuitry may also be programmable to couple one of a plurality of data inputs to the output driver to operate an input/output device in either a single-ended mode or a differential mode.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.

Abstract: Embodiments provide input/output devices having programmable logic that is programmable to operate input/output devices in one of two drive modes. In various embodiments, to operate an input/output device in a first drive mode, logic circuitry is programmable to couple a reference voltage to a gate of a transistor element of an output driver. In various embodiments, to operate an input/output device in a second drive mode, the logic circuitry is programmable to couple a bias voltage to the gate of the transistor element of the output driver. In various embodiments, the logic circuitry may also be programmable to couple one of a plurality of data inputs to the output driver to operate an input/output device in either a single-ended mode or a differential mode.

Abstract: Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed.

Abstract: Embodiments of programmable delay line circuits are disclosed herein. The delay line circuit may comprise a first multiplexer having a first input coupled with an input line; a second multiplexer having a first input, and a second input coupled with an output of the first multiplexer, and an output coupled with a second input of the first multiplexer; a third multiplexer having a first input coupled with the output of the second multiplexer, a second input coupled with the input line, and an output coupled with an output line; a first control gate coupled with the third multiplexer to control the third multiplexer; and a second control gate coupled with the second multiplexer to control the second multiplexer; wherein the first and second control gates selectively control the second and third multiplexer, responsive to a delay value encoded in Gray Code.

Abstract: Embodiments provide systems, methods, and integrated circuits having a calibration structure with a calibration component and a measurement structure coupled to the calibration component. The measurement structure is configured to vary a current through the calibration component until a voltage of the calibration component equals an operation voltage. The variable current is a function of at least the operation voltage and a resistance of a resistor external to the measurement structure.

Abstract: Embodiments of crossbar devices constructed with Micro-Electro-Mechanical Systems (MEMS) switches are disclosed herein. A crossbar device may comprise m input terminals, n output terminals, n control lines and m×n MEMS switches coupled to the n control lines to selectively couple the m input terminals to the n output terminal. Each of the MEMS switches may comprise a contact node coupled to one of the m input terminals, a cantilever coupled to one of the n output terminals, a control node coupled to one of the n control lines to electrostatically control the cantilever to contact the contact node or be away from the contact node using electrostatic attractive or repulsive force respectively. The cantilever and the contact node are configured to remain in contact by molecular adhesion force, after the cantilever has been electrostatically controlled to contact the contact node, and the electrostatic attractive force has been removed. Other embodiments may be described and claimed.

Abstract: Embodiments provide methods, systems, and apparatuses including combinatorial or reconfigurable circuitry having input/output (I/O) circuitry with an I/O terminal and an input buffer. The I/O terminal receives a receive signal at a receive signal level that was transmitted from another integrated circuit at a transmitted signal level which is either a first or a second different signal level. The input buffer compares the receive signal to one or more reference signals to generate an input signal corresponding to the transmitted signal level based at least in part on the result of the comparison, even if the receive signal is received at a third signal level in between the first and the second signal level.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.

Abstract: A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

Abstract: A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

Abstract: A method and apparatus for clock generation and distribution in an emulation system is described. The present invention provides a method and apparatus for generating a derived clock signal with a circuit having a look up table. A counter circuit counts clock cycles and provides an index into the look up table. A frequency divider circuit may be used between the counter circuit and a base clock signal to provide an intermediate clock signal with a frequency that is less than the frequency of the base clock signal. In one embodiment, a selection circuit is provided to select between the base clock signal and an external clock signal.

Abstract: A number of enhanced logic elements (LEs) are provided to form a FPGA. Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved FPGA further comprises a network of crossbars, a context bus, a scan register, and a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.

Abstract: A regionally time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic devices with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic devices are reconfigurable to emulate a circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic devices, with the at least one signal routing clock being independent of the at least one user clock.

Abstract: A number of enhanced logic elements (LEs) are provided to form a reconfigurable integrated circuit (IC). Each enhanced LE comprises a multiple input-single output truth table, and a complementary pair of master-slave latches having a data, a set and a reset input. Each enhanced LE further comprises a plurality of multiplexers and buffers, and control logic. Additionally, the improved IC may further comprises a scalable network of crossbars, a context bus, a scan register, and/or a plurality of trigger circuitry. As a result, each LE may be individually initialized, its signal state frozen momentarily, the frozen state be read, trace data be output, and trigger inputs be conditionally generated, making the IC particularly suitable for circuit design emulation. Furthermore, the enhanced LEs may be used for “level sensitive” as well as “edge sensitive” circuit design emulations.

Abstract: A scalable emulation system is disclosed. The basic embodiment of the emulation system includes a number of logic boards with logic chips that are reconfigurable to emulate circuit elements of a circuit design. The basic embodiment further includes a number of interconnect boards coupled to at least the logic boards. Each of the interconnect boards includes interconnect chips that are reconfigurable to selectively interconnect the logic chips of different ones of the logic boards. Additionally, at least each of a subset of the interconnect boards includes a number of expansion connectors for facilitating expansion of the emulation system in one or more selected ones of expansion orientations through coupling of at least one or more substantial replicates of the basic embodiment.