Patents by Inventor Jean Barret

Jean Barret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7054171
    Abstract: The invention concerns a control circuit (20) of a switch (6) chopping a voltage supply of a primary winding of a power converter transformer, comprising means (45) for detecting the current in the switch in closed state after a predetermined time following each closure of said switch, and a comparator (40) of said current relative to a threshold (Ilim), the result of said comparator being taken into account for a predetermined time interval close to the beginning of a closing cycle of said chopping switch.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: May 30, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Alain Bailly, Jean Barret
  • Patent number: 6057577
    Abstract: The present invention relate to a device of protection against voltage gradients of a monolithic component including a vertical MOS power transistor and logic circuits. The protection circuit has an N-type substrate corresponding to the drain of the MOS transistor, and logic components being realized in at least one P-type well formed in the upper surface of the substrate. Each of the N-type regions connected to the ground of the logic circuit, or to a node of low impedance with respect to the ground, is in series with a resistor.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: May 2, 2000
    Assignee: STMicroelectronics S.A.
    Inventors: Jean Barret, Antoine Pavlin, Pietro Fichera
  • Patent number: 6054740
    Abstract: The present invention relates to a protection device for a component including a vertical MOS power transistor and logic components. The protection device includes a first zener diode, a first terminal of which corresponds to the substrate and a second terminal of which corresponds to a region of the second type of conductivity formed in the substrate. It also includes a second zener diode of the same type of conductivity as the first zener diode but of higher avalanche voltage, the second terminals of both zener diodes being connected to a circuit for starting the power transistor via a logic circuit which only becomes conductive when one of its inputs is high and distinct from the other input.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: April 25, 2000
    Assignee: STMicroelectronics S.A.
    Inventor: Jean Barret
  • Patent number: 5780895
    Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 14, 1998
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean Barret, Daniel Quessada
  • Patent number: 5563436
    Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 8, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean Barret, Daniel Quessada
  • Patent number: 5543645
    Abstract: A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: August 6, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean Barret, Daniel Quessada