Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.

Abstract: The invention relates to an optoelectronic device comprising a photonic interposer comprising: a photonic circuit containing at least one active optical component, an upper interconnect layer comprising at least one upper control portion, a lower interconnect layer comprising at least one lower control portion and lower intermediate portions, at least one TSV directly connecting the upper control portion to the lower control portion, conductive vias connecting the lower intermediate portions to the active optical component; at least one first microelectronic chip joined to the upper face of the photonic interposer; a second microelectronic chip joined to the lower face of the photonic interposer, and connected to the lower control portion and to the lower intermediate portions.

Abstract: A spin Qbits quantum device includes a substrate of the semiconductor on insulator type provided with a surface semiconductor layer disposed on an insulating layer, the insulating layer being arranged on an upper face of a semiconductor support layer, and a component formed of one or more quantum islands extending in the surface layer and one or more gate electrodes for electrostatic control of the islands. Front gate electrodes are disposed on the surface layer, and the component includes a back electrostatic control gate formed of a conductive layer lining lateral walls and a bottom of an opening passing through the support layer from a lower face opposite the upper face up to the insulating layer. The conductive layer is disposed at the bottom of the opening in contact with the insulating layer, the conductive layer being disposed in contact with the support layer at the lateral walls.

Abstract: An integration structure for connecting a plurality of semiconductor devices, includes a substrate, a first face and a second face for receiving the semiconductor devices. At the first surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. At the second surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. The integration structure includes at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting conductive track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.

Abstract: An electronic device includes a first surface and a second surface opposite the first surface and intended to connect a first electronic component to a second electronic component located on the first surface by at least one conductor track, the conductor track including a plurality of sections disposed one after the other in such a way as to form the conductor track, each section being constituted of a superconducting material chosen in such a way as to form with the section that follows it, if such a section exists, and the section that precedes it, if such a section exists, an acoustic mismatching interface (or Kapitza interface).

Abstract: A method is provided for localised deposition of a material over an element, including deposition of a portion of the material over a portion of a surface of a support; positioning of a portion of the element against the portion of the material; annealing of the material portion increasing, at the end of the treatment, the adhesion force of the material against the portion of the element, the materials of the portion of the element and of the portion of the surface of the support being selected such that the adhesion of the material against the portion of the element is, at the end of the annealing, higher than that of the material against the portion of the surface of the support; and separation of the element and the support at the interface between the material and the portion of the surface of the support, the material remaining secured to the portion of the element.

Abstract: The invention relates to an optoelectronic device 1 comprising: a photonic interposer 10 comprising: a photonic circuit 14.1 containing at least one active optical component 14.2, an upper interconnect layer 11, comprising at least one upper control portion 11.2, a lower interconnect layer 17, comprising at least one lower control portion 17.2, and lower intermediate portions 17.3, at least one TSV 18.1 directly connecting the upper control portion 11.2 to the lower control portion 17.2, conductive vias 15.1 connecting the lower intermediate portions 17.3 to the active optical component 14.2; at least one first microelectronic chip 20, joined to the upper face 10a of the photonic interposer; a second microelectronic chip 30, joined to the lower face 10b of the photonic interposer, and connected to the lower control portion 17.2 and to the lower intermediate portions 17.3.

Abstract: A spin qubit quantum device, comprising: a semiconductor portion comprising a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, and wherein the first gate is not aligned with the second gates.

Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.

Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.

Abstract: Method for producing an interface for assembling temporarily a microelectronic support and a handle, comprising at least the formation of a first layer comprising at least one material capable of releasing at least one chemical species under the action of a physical-chemical treatment, the formation of a second layer comprising at least one material capable of receiving the at least one chemical species so as to cause its embrittlement, and the embrittlement of the interface by application of a heat treatment, such that the at least one species is released from the first layer and reacts with all or part of the material of the second layer.

Abstract: A process for exposing at least one region of a face, known as the front face, of an electronic device, the process including the following steps: A bonding step for a cover (600) to the front face, the bonding being undertaken such that the cover (600) forms a closed cavity (650) with the region, advantageously hermetically sealed; Formation of an encapsulation coating (700), of thickness E1, covering the front face and the cover (600); A thinning step for the encapsulation coating (700), the thinning step including removal of a removal thickness E2, less than the thickness E1, of the encapsulation coating (700), the removal thickness E2 being adjusted such that an opening is formed in the cover (600).

Abstract: A process for exposing at least one region of a face, known as the front face, of an electronic device, the process including the following steps: A bonding step for a cover (600) to the front face, the bonding being undertaken such that the cover (600) forms a closed cavity (650) with the region, advantageously hermetically sealed ; Formation of an encapsulation coating (700), of thickness E1, covering the front face and the cover (600); A thinning step for the encapsulation coating (700), the thinning step including removal of a removal thickness E2, less than the thickness E1, of the encapsulation coating (700), the removal thickness E2 being adjusted such that an opening is formed in the cover (600).

Abstract: Method for producing an interface for assembling temporarily a microelectronic support and a handle, comprising at least: the formation of a first layer comprising at least one material capable of releasing at least one chemical species under the action of a physical-chemical treatment, the formation of a second layer comprising at least one material capable of receiving the at least one chemical species so as to cause its embrittlement, the embrittlement of the interface by application of a heat treatment, such that the at least one species is released from the first layer and reacts with all or part of the material of the second layer.

Abstract: An electronic chip and a method of making thereof is provided, where the electronic chip includes at least: an electronic circuit arranged at a front face of a substrate; a first protective layer arranged on a rear face of the substrate; a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit; a second protective layer covering at least the resistive element; and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

Abstract: Electronic chip comprising at least: an electronic circuit arranged at a front face of a substrate; a first protective layer arranged on a rear face of the substrate; a resistive element arranged on the first protective layer and facing at least one part of the electronic circuit, mechanically supported by the first protective layer and connected electrically and/or in an inductive manner to the electronic circuit; a second protective layer covering at least the resistive element; and in which the first protective layer comprises at least one dielectric material having a resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.

Abstract: The present invention relates to pulverulent materials suitable for storing hydrogen, and more particularly to a method of preparing such a material, in which: (A) a composite metallic material having a specific granular structure is prepared by co-melting the following mixtures: a first metallic mixture (m1), which is an alloy (a1) of body-centered cubic crystal structure, based on titanium, vanadium, chromium and/or manganese, or a mixture of these metals in the proportions of the alloy (a1); and a second mixture (m2), which is an alloy (a2), comprising 38 to 42% zirconium, niobium, molybdenum, hafnium, tantalum and/or tungsten and 56 to 60 mol % of nickel and/or copper, or else a mixture of these metals in the proportions of the alloy (a2), with a mass ratio (m2)/(m1+m2) ranging from 0.1 wt % to 20 wt %; and (B) the composite metallic material thus obtained is hydrogenated, whereby the composite material is fragmented (hydrogen decrepitation).

Abstract: The present invention relates to pulverulent materials suitable for storing hydrogen, and more particularly to a method of preparing such a material, in which: (A) a composite metallic material having a specific granular structure is prepared by co-melting the following mixtures: a first metallic mixture (m1), which is an alloy (a1) of body-centred cubic crystal structure, based on titanium, vanadium, chromium and/or manganese, or a mixture of these metals in the proportions of the alloy (a1); and a second mixture (m2), which is an alloy (a2), comprising 38 to 42% zirconium, niobium, molybdenum, hafnium, tantalum and/or tungsten and 56 to 60 mol % of nickel and/or copper, or else a mixture of these metals in the proportions of the alloy (a2), with a mass ratio (m2)/(m1+m2) ranging from 0.1 wt % to 20 wt %; and (B) the composite metallic material thus obtained is hydrogenated, whereby the composite material is fragmented (hydrogen decrepitation).

Abstract: The present invention relates to pulverulent materials suitable for storing hydrogen, and more particularly to a method of preparing such a material, in which: (A) a composite metallic material having a specific granular structure is prepared by co-melting the following mixtures: a first metallic mixture (m1), which is an alloy (a1) of body-centered cubic crystal structure, based on titanium, vanadium, chromium and/or manganese, or a mixture of these metals in the proportions of the alloy (a1); and a second mixture (m2), which is an alloy (a2), comprising 38 to 42% zirconium, niobium, molybdenum, hafnium, tantalum and/or tungsten and 56 to 60 mol % of nickel and/or copper, or else a mixture of these metals in the proportions of the alloy (a2), with a mass ratio (m2)/(m1+m2) ranging from 0.1 wt % to 20 wt %; and (B) the composite metallic material thus obtained is hydrogenated, whereby the composite material is fragmented (hydrogen decrepitation).

Abstract: The invention relates to a method for preparation of a material adapted to reversible storage of hydrogen, including steps consisting of providing a first powder of a magnesium-based material, hydrogenating the first powder to convert at least part of the first powder into metal hydrides, mixing the first hydrogenating powder with a second powder additive, the proportion by mass of the second powder in the mix obtained being between 1% and 20% by mass, wherein the additive is formed from an alloy with a centred cubic structure based on titatnium, vanadium and at least one other metal chosen from chromium or manganese, and grinding the mix of first and second powders.