Abstract: This invention relates to a matrix for switching between two time-division multiplex groups, including three areas for buffering the data arriving in multiplex onto input junctions, which issue these data in multiplex to output junctions according to an assignment of each time slot of an input multiplex to a time slot of an output multiplex, a first area being meant for receiving the data relative to the transmissions as they are issued by a series-to-parallel converter receiving the input junctions and for enabling, at least when the data belong to a transmission channel including several time slots of a same multiplex, a transfer of the data to one of the two other buffer areas according to the parity of the multiplex frame it contains.

Abstract: A device for transferring binary data between a time-division multiplex and a RAM includes circuitry for assigning, for each time slot of the multiplex, a logical channel number. This enables two HDLC controllers, respectively for transmission and reception, to be shared between all the channels of the multiplex.

Abstract: A read/write memory cell comprises a first switch having one input which constitutes the data input-output of the cell and another input connected to a loop circuit comprises a first inverter, a second inverter and a second switch. The first and second switches are controlled in such a way that on a write operation the first is closed and the second open. In the absence of any write or read operation the first switch is open and the second switch is closed. On a read operation both switches are closed. A read/write memory of N words each of P bits is obtained by associating N.times.P cells of this kind in a matrix comprising N rows and P columns.