Abstract: The method enables transmission of a digital service channel by means of the parity channel of a digital bit stream transmitted in a parity checking code with parity words inserted at specific times by modifying certain parity words violating the parity checking code parity law. It consists in modifying spaced groups of even number of consecutive parity words so as not to disrupt analog detection of line errors. A digital service channel insertion circuit is included among the component parts of an MBIPIC type encoder whereby the data of a digital bit stream is transmitted by consecutive code words each formed of a block of data bits completed by a parity bit and an inversion bit.

Abstract: The invention relates to input and output circuits for multiplexing equipment, especially the kind used in telephone systems where nominally identical clocking signals have natural deviations of timing (called "plesiochronous" signals). The invention uses the "justification" principle to ensure the clock synchronization of plesiochronous digital signals. A buffer memory, with independent writing and reading capabilities, is formed of two first in-first out or "FiFo" memories connected in series. The request signal for a "justification" is made when a connection is completed between an IR (Input-Ready) output of the second FiFo memory and an input SO (Shift-Out) of the first FiFo memory, if there is an undesirable phase shift between the input and output clocking system.