Abstract: The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high frequency filter is in operation. If operating, a status register is set which a microcontroller can poll to determine if an attack has been attempted. A microcode programmer can then control what sequence of events occur once the register has been set. Alternatively, detection of operation of the high frequency filter could automatically trigger a reset or interrupt of the microcontroller.

Abstract: The present invention provides a means for clearing or wiping the contents of a RAM array without the need for overly large transistors and without experiencing current spikes by using a progressive row-by-row clearing operation. In reference to FIGS. 4 and 5, progressive row clearing is achieved by the addition of a transistor (72) in series with the row RAMWIPE transistor (e.g. transistor 69) in each row. Transistor 72 is gated by a signal PRS (Previous Row Select). PRS for a given row will be asserted or enabled only when the previous row in the array is also selected or enabled. A given row is only selected for clearing in a wipe operation when both a RAMWIPE signal and a PRS (previous row select) signal are asserted. The next row, therefore, is not cleared until the previous row is cleared.

Abstract: A portable data carrier, suitable for operation in either a contacted or a contactless mode, includes a clock signal input pad and a clock detection circuit. The clock input pad includes an output that is coupled to a selection circuit having a first input and a second input. An input for the selection circuit is coupled to the output of the clock detection circuit. The microprocessing unit follows the clock being transmitted via the clock input pad in the contacted mode of operation if the clock detection circuit confirms presence of such a clock signal. Otherwise, the contactless mode of operation is chosen, where the microprocessing unit follows a radio frequency clock.

Abstract: A portable data carrier (10) embodies an integrated circuit (12) with an EEPROM (24). The EEPROM has a number of rows of memory cells (32, 38, 44) each having outputs respectively coupled to bit lines (50, 54, 56), and control inputs coupled to a common control line (132). The bit lines each include a latch (60, 62, 64) that is set to provide a programming voltage (VPP) during write mode. The bit lines have serial switches (78, 80, 82) that break continuity when writing to the latches. The bit line latches are made transparent to the bit lines during read mode. The common control line is coupled through a programming transistor (130) to an erase line (72). The erase line must be driven to a programming voltage during erase mode. The erase line uses one of the bit line latches to provide its programming voltage.

Abstract: A voltage protection arrangement (10) comprises a semiconductor substrate (12) having at least two electrical conductors (16,18,20) adjacent an edge of the substrate. An aperture (22) extends from the edge towards a point between the two electrical conductors. The aperture (22) reduces conductance between the two electrical conductors (16,18) in a region adjacent the edge of the substrate (12), such that if an excess voltage occurs between the two conductors (16,18), a reduced current flows in the region.

Abstract: An EPROM memory transistor programming arrangement is disclosed in which programming voltage for a memory transistor is applied via a load line of series connected N-channel MOS transistors which are controlled by low voltage NAND gate having low voltage address, write select and data inputs, through a high voltage inverter. The arrangement may be implemented entirely by N-channel MOS transistors which enables a compact silicon implementation and requires no separate BVDSS breakdown protection.

Abstract: There is described a low voltage sense amplifier for an EPROM memory transistor which has a low voltage inverter coupled to the memory transistor. The inverter receives a selectable low reference voltage as its power supply and the same reference voltage is fed as a precharge voltage, prior to reading an EPROM bit, to the input of the inverter.

Abstract: A stepwise approximation of a sinewave is generated by inputting different values representing different points on the waveform from a ROM (6) to a step duration counter (5). At the end of each step, a step counter (7) is incremented causing the ROM to input the next value. An up/down counter (3) is also incremented at the end of each step and caused to count in the opposite direction after a preset number of steps. The counter (3) produces an output representing the sinewave where the amplitude of all of the steps are equal but where their duration varies to produce the sinewave shape and this output is then passed to a D/A converter (9). An oscillator (1) is used to provide clock pulses to the step duration counter (5) and also to the up/down counter (3). Two such sinewave generators can be used in a dualtone multifrequency dialling circuit.

Abstract: A low power, single pin CMOS oscillator has been provided which exhibits good frequency stability with voltage supply variations. The oscillator uses a capacitor which is connected to the inputs of two inverters. One inverter is used to drive a P-channel transistor and the other inverter is used to drive an N-channel transistor. Both P-channel and N-channel transistors are connected in series and provide an output from a junction formed between the two transistors. A latch is connected to the junction formed between the two transistors and the output of the latch is coupled to the capacitor to charge and discharge it.