Abstract: An electrically erasable and reprogrammable non volatile memory cell is disclosed which is implemented in CMOS polycrystalline silicon gate transistor technology and comprises a p-channel MOS transistor the gate of which forms a first portion of a floating electrode. A second portion of said floating electrode has a substantially larger surface than the two other portions and is placed on a field oxide layer. A third portion of the floating electrode is placed on an injection oxide layer which is thinner than the gate oxide layer of the transistor. A p.sup.- -doped well is formed under said third portion and is connected electrically to a write control electrode. An erase control electrode is arranged opposite the second portion of the floating electrode. The disclosed memory cell can be erased and reprogrammed through relatively low control voltages of a single polarity and these processes lead only to very small current consumption.

Abstract: The invention relates to non-volatile electrically erasable and reprogrammable memories produced by CMOS technology.According to the invention, each memory element comprises only a single p-channel transistor having a polycrystalline silicon floating gate capacitively coupled to a control electrode. The thicknesses of injection oxide and gate oxide are such that the element can be programmed by avalanche of the drain-substrate junction and erased by field emission of electrons from the floating gate towards the substrate.All the voltages required can be generated on the circuit of the memory from a battery voltage of 1.5 volts.

Abstract: An integrated control device for controlling a device such as a LED display or a miniature stepping motor for an electronic watch comprises at least one insulated-gate field effect transistor for controlling the supply of current to the element. The gate of the F.E.T. is connected to a control circuit including a voltage multiplier comprising a series-connected chain of rectifiers and a plurality of capacitors connected between the respective junctions between rectifiers and alternate inputs. High frequency signals of opposite phase are supplied to the inputs under control of an input control signal. Circuit means are provided for starting the action of the voltage multiplier at the beginning of an input control signal and for short-circuiting the output of the control circuit at the end of an input control signal.

Abstract: Electronic timepiece having an electro-optic passive display cell comprising an oscillator used as a time base and an electronic control circuit of its several functions. The electronic circuit is operable by means of a stationary key or switch, having a capacitive action, carried by the glass or crystal of the timepiece. The stationary key is fed by the oscillator through a fixed or non-variable condenser. A conductive element is interposed between the stationary key and the display cell, the conductive element constituting one of the electrodes of the fixed condenser. The purpose of this arrangement is to eliminate the influence of a parasitic condenser constituted by the electrodes of the display cell and the electrode of the stationary key.

Abstract: An electronic watch control device for manual actuation is disclosed. It comprises a capacitive sensor including a conductive layer on the inner surface of the watch-glass, which is actuated by placing a finger-tip on the outer side of the watch-glass. The sensor is part of a capacitive voltage divider to which a high frequency voltage is applied. Synchroneous detection means are arranged for detecting the high-frequency voltage drop across the sensor in synchronism with the high-frequency. Comparison means are provided for comparing the value of the said voltage drop to a reference voltage and producing a control signal depending on the condition of the sensor.

Abstract: An active circuit is disclosed including an integrated circuit having at least one amplification stage comprising an FET. At least one negative feedback transistor is provided of the same conduction type as the amplifying transistor, with the drain-to-source path of the negative feedback transistor coupled in series between the drain and gate of the amplifying transistor. At least one biasing transistor of the same conduction type as the amplifying transistor are provided to bias the gate of the negative feedback transistor. The drain of the at least one biasing transistor is connected to a current source furnishing a current having a given ratio to the power supply current of the amplifying transistor. This circuit permits precise control of the small-signal resistance of the feedback transistor.

Abstract: A device for transmission of information by pulse code frequency shift modulation. The device incorporates a phase-locked superheterodyne receiver including a single voltage controlled oscillator, and a demodulator including a phase comparator and a phase shifter. The intermediate frequency is equal to one half the input signal frequency shift. The comparator compares the phases of the intermediate frequency signal and of a signal of the same frequency derived from the voltage controlled oscillator to provide a message output.