Abstract: In one aspect, a data race condition is detected based on an address of a variable shared by at least first and second threads for executing the program code, the shared variable address being stored in a hardware table. Detection of the data race condition in the program code is reported. In another aspect, at least first and second threads for executing the program code are synchronized based on an address of a variable shared by the threads and stored in a hardware table.

Abstract: In one aspect, a value of a variable shared by multiple threads for executing the program code is stored in a thread-local variable. A data race condition is detected based on a comparison of values of the shared variable and the thread-local variable. Detection of the data race condition is reported. In another aspect, a machine-readable instruction to store in a thread-local variable a value of a variable shared by multiple threads for executing the program code is generated. A machine-readable instruction to detect a data race condition based on a comparison of values of the shared variable and the thread-local variable is generated. The machine-readable instructions are stored in a machine-readable medium.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.

Abstract: Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor are disclosed. In an example, a compiler inserts decision code into the object code to thereby cause the in-order processor to operate like an out of order processor to operate with respect to at least some memory access instructions. The decision code determines at run time of the object code whether a load instruction is a likely cache hit. Based on that determination, the decision code causes the in-order processor to execute a use instruction at a first time if the load instruction is a likely cache hit, and to execute a copy of the use instruction at a second, later time if the load instruction is not a likely cache hit.

Abstract: A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to the first register, whether a corresponding element from data storage matches a corresponding element of the first register.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor are disclosed. In an example, a compiler inserts decision code into the object code to thereby cause the in-order processor to operate like an out of order processor to operate with respect to at least some memory access instructions. The decision code determines at run time of the object code whether a load instruction is a likely cache hit. Based on that determination, the decision code causes the in-order processor to execute a use instruction at a first time if the load instruction is a likely cache hit, and to execute a copy of the use instruction at a second, later time if the load instruction is not a likely cache hit.