Patents by Inventor Jean Garcia

Jean Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959108
    Abstract: The present invention provides engineered protease polypeptides and compositions thereof. The engineered protease polypeptides have been optimized to provide improved activity, improved thermostability, protease stability, autolytic stability, and stability under a range of pH conditions, including acidic (pH<7) and basic (pH>7) conditions. The invention also relates to the use of the compositions comprising the engineered protease polypeptides for therapeutic and/or nutritional purposes. The present invention also provides polynucleotides encoding the engineered protease polypeptides, as well as methods for making the engineered polynucleotides and protease polypeptides.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 16, 2024
    Assignees: Codexis, Inc., Societe des Produits Nestle S.A.
    Inventors: Chinping Chng, Nikki Dellas, Ravi David Garcia, Moulay Hicham Alaoui Ismaili, Kristen Jean Vallieu, Kerryn McCluskie
  • Patent number: 11917097
    Abstract: Methods and systems described in this disclosure allow customers to quickly be authenticated. In some embodiments, a device and a user verifier are associated with a user profile. When a call is received from the device, the user may be requested to input the user verifier. After verifying that the device is unique to the user and that the user verifier matches the user verifier associated with the user profile, the user may be authenticated to the call or activity.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: February 27, 2024
    Assignee: United Services Automobile Association (USAA)
    Inventors: Patricio H. Garcia, Amanda Jean Segovia, Hector J. Castillo, Susan Cass Mason, Robert Craig Korom
  • Publication number: 20240014809
    Abstract: A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 11, 2024
    Inventors: Laurent Jean Garcia, Marc Houdebine
  • Patent number: 11190236
    Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 30, 2021
    Assignee: STMICROELECTRONICS SA
    Inventors: Marc Houdebine, Laurent Jean Garcia
  • Publication number: 20210126672
    Abstract: An embodiment near-field communication device using active load modulation, in card emulation mode and intended to communicate with a reader, comprises a digital phase-locked loop configured to generate a carrier signal, having an oscillator configured to generate the carrier signal in a manner controlled by an analog control signal, a feedback circuit configured to generate a digital control signal, a digital-to-analog converter configured to convert the digital control signal into the analog control signal, and an integrator assembly configured to integrate the analog control signal.
    Type: Application
    Filed: October 26, 2020
    Publication date: April 29, 2021
    Inventors: Marc Houdebine, Laurent Jean Garcia
  • Patent number: 7902859
    Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wher
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: March 8, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Nicolas Ricard, Laurent Jean Garcia
  • Publication number: 20100097093
    Abstract: Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wher
    Type: Application
    Filed: October 15, 2009
    Publication date: April 22, 2010
    Applicant: STMicroelectronics S.A.
    Inventors: Nicolas Ricard, Laurent Jean Garcia
  • Patent number: 5211426
    Abstract: Irrigation apparatus comprising, in combination, a main water feed pipe made of elastically deformable material and at least one branch including a needle having a sharp end and sufficiently stiff to be capable of being connected to the main pipe by being forced through the wall thereof, wherein a portion of the inside surface of the wall of the main pipe includes an extra thickness of a resiliently deformable rubber material of hardness which is much less than that of the material constituting the wall of the pipe and which is suitable for sealing orifices formed through its bulk.
    Type: Grant
    Filed: September 25, 1990
    Date of Patent: May 18, 1993
    Assignee: Hutchinson
    Inventors: Rene J. Guignard, Jean Garcia
  • Patent number: 3938140
    Abstract: The invention relates to data display devices having a segmented structure. It provides a display device whose adjacent coplanar segments are divided up into complementary areas respectively connected to excitation units controlled simultaneously in such manner as to produce, in the absence of break down, a homogeneous display of the segments. The invention applies to display by elementary sources of light or by liquid crystals and other materials having electro-optical properties.
    Type: Grant
    Filed: May 6, 1974
    Date of Patent: February 10, 1976
    Assignee: Thomson-CSF
    Inventors: Jean Garcia, Michel Hareng, Eugene Leiba