Patents by Inventor Jean Kodama
Jean Kodama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120159042Abstract: A data storage device is disclosed comprising a non-volatile memory (NVM) including a plurality of sectors each having a sector size. An access command is received from a host, wherein the access command identifies a plurality of host blocks having a host block size less than the sector size. A plurality of the host blocks are mapped to a target sector. When the target sector spans an encryption zone boundary defined by the host blocks, a NVM command is generated identifying a first key corresponding to a first encryption zone and a second key corresponding to a second encryption zone. The NVM command is executed as a unitary operation to access a first part of the target sector using the first key and access a second part of the target sector using the second key.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: GLENN A. LOTT, JEAN KODAMA, DANNY O. YBARRA
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Patent number: 8099470Abstract: A storage networking device provides remote direct memory access to its buffer memory, configured to store storage networking data. The storage networking device may be particularly adapted to transmit and receive iSCSI data, such as iSCSI input/output operations. The storage networking device comprises a controller and a buffer memory. The controller manages the receipt of storage networking data and buffer locational data. The storage networking data advantageously includes at least one command for at least partially controlling a device attached to a storage network. Advantageously, the storage networking data may be transmitted using a protocol adapted for the transmission of storage networking data, such as, for example, the iSCSI protocol. The buffer memory advantageously is configured to at least temporarily store at least part of the storage networking data at a location within the buffer memory that is based at least in part on the locational data.Type: GrantFiled: March 31, 2009Date of Patent: January 17, 2012Assignee: Promise Technology, Inc.Inventors: Jean Kodama, Michael Morrison
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Patent number: 7869355Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.Type: GrantFiled: December 1, 2008Date of Patent: January 11, 2011Assignee: Promise Technology, Inc.Inventors: Jean Kodama, Li Xu
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Publication number: 20090248830Abstract: A storage networking device provides remote direct memory access to its buffer memory, configured to store storage networking data. The storage networking device may be particularly adapted to transmit and receive iSCSI data, such as iSCSI input/output operations. The storage networking device comprises a controller and a buffer memory. The controller manages the receipt of storage networking data and buffer locational data. The storage networking data advantageously includes at least one command for at least partially controlling a device attached to a storage network. Advantageously, the storage networking data may be transmitted using a protocol adapted for the transmission of storage networking data, such as, for example, the iSCSI protocol. The buffer memory advantageously is configured to at least temporarily store at least part of the storage networking data at a location within the buffer memory that is based at least in part on the locational data.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: iSTOR NETWORKS, INC.Inventors: Jean Kodama, Michael Morrison
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Patent number: 7512663Abstract: Mechanisms and processes for directly storing data into the memory of a storage device using the iSCSI protocol are described. One mechanism includes a transmitting device that encodes data to be stored in an iSCSI protocol data unit. Also encoded is buffer locational data that indicates, directly or indirectly, one or more memory addresses of where the data is to be stored within the buffer memory of a receiving device. The buffer locational data is encoded using standard fields within the iSCSI protocol data unit, such as the Target Transfer Tag. A receiving device decodes the buffer locational data and stores the received data at the memory locations specified by the buffer locational data.Type: GrantFiled: February 18, 2004Date of Patent: March 31, 2009Assignee: iStor Networks, Inc.Inventors: Jean Kodama, Michael Morrison
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Publication number: 20090073884Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.Type: ApplicationFiled: December 1, 2008Publication date: March 19, 2009Applicant: ISTOR NETWORKS, INC.Inventors: Jean Kodama, Li Xu
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Patent number: 7460473Abstract: Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.Type: GrantFiled: February 17, 2004Date of Patent: December 2, 2008Assignee: Istor Networks, Inc.Inventors: Jean Kodama, Li Xu
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Patent number: 7362702Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 29, 2002Date of Patent: April 22, 2008Assignee: QLOGIC, CorporationInventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20080008202Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a viral entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 7292567Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 31, 2002Date of Patent: November 6, 2007Assignee: QLogic CorporationInventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20070183421Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: March 30, 2007Publication date: August 9, 2007Inventors: William Terrell, Tracy Edmonds, Wayland Jeong, Eric Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 7200144Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: GrantFiled: October 18, 2001Date of Patent: April 3, 2007Assignee: Qlogic, Corp.Inventors: William C. Terrell, Tracy Edmonds, Wayland Joeng, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030189936Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 31, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030191857Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 30, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Publication number: 20030189930Abstract: A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction.Type: ApplicationFiled: October 29, 2002Publication date: October 9, 2003Inventors: William C. Terrell, Tracy Edmonds, Wayland Jeong, Eric Russell Peterson, Jean Kodama, Harun Muliadi, Norman Chan, Rexford Hill, Michael Nishimura, Stephen How
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Patent number: 5276807Abstract: Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIFO buffer to allow rapid sequential transfers; while also providing a flexible input/output configuration allowing both single-ended and differential mode connections.Type: GrantFiled: July 20, 1990Date of Patent: January 4, 1994Assignee: Emulex CorporationInventors: Jean Kodama, Borden T. Moller, Paul R. Nitza