Patents by Inventor Jean L. J. Calvignac

Jean L. J. Calvignac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4779269
    Abstract: Method for transporting asynchronous data and synchronous non coded information NCI bits on a common channel operating at (n+1)/T bits per second, in slot of duration T containing n+1 bits, the data and NCI portions of the bit stream to be transported being delimited by a flag having a specific pattern which cannot be simulated by the data bits. During the periods where there is an NCI activity, the first n bits of the slot are used for transporting NCI bits and the last bit is used for transporting an additional data bit, if the said first n bits are different from the flag pattern and said last bit is set to a first binary value (0) if said first n bits are similar to the flag pattern. During the periods where there is no NCI activity, data bits are sent in at least one slot delimited by two slots, the first n bits of which are set to the flag pattern and the last bit of which is set to the second binary value (1).
    Type: Grant
    Filed: March 24, 1987
    Date of Patent: October 18, 1988
    Assignee: International Business Machines Corporation
    Inventors: Michel Bouillot, Jean L. J. Calvignac, Jean M. L. Munier
  • Patent number: 4760573
    Abstract: A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links.
    Type: Grant
    Filed: November 13, 1986
    Date of Patent: July 26, 1988
    Assignee: International Business Machines Corp.
    Inventors: Jean L. J. Calvignac, Jacques M. Clement Feraud, Jean-Marie L. Munier
  • Patent number: RE34896
    Abstract: A multiplex interface for interconnecting the line scanning means (1) of a communication controller to user lines via transmit and receive synchronous multiplex links. Both data and control bits are exchanged in synchronous frames wherein at least two slots are assigned to each user line, the structure of the two slots is identical for all types of user lines and includes an n-bit data slot having a variable number x of valid bits depending upon the line speed of the user line assigned to the data slot and indicated by a variable delimiter pattern comprising a first delimiting bit set at a first binary value (1) adjacent to the data bits and (n--x--1) bits set at the second binary value (0) adjacent to said first delimiting bit, and an n-bit control slot having a first bit used as a global validation bit in case the data slot comprises n valid bits (x.dbd.
    Type: Grant
    Filed: May 29, 1991
    Date of Patent: April 4, 1995
    Assignee: International Business Machines Corporation
    Inventors: Jean L. J. Calvignac, Jacques M. C. Feraud, Jean-Marie L. Munier