Patents by Inventor Jean Lajzerowicz

Jean Lajzerowicz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for etching and depositing integrated circuit interconnections and contacts
    Patent number: 5354711
    Abstract: Process for producing an integrated circuit stage formed from a dielectric layer (1) covering interconnection lines (5) and connection points (4), which connect the said lines (5) to conductive parts (6) on the opposite side of the dielectric layer (1). The process consists of forming all the dielectric layer (1) during a single step and then successively etching cavities at the locations of the connection points and the interconnection lines by means of two successively positioned masks and then filling the cavities in a single step with conductive material in order to simultaneously form connection points (4) and interconnection lines (5).
    Type: Grant
    Filed: July 8, 1993
    Date of Patent: October 11, 1994
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Michel Heitzmann, Jean Lajzerowicz, Philippe LaPorte