Patents by Inventor Jean-Luc Jaffard

Jean-Luc Jaffard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8575712
    Abstract: A camera module includes a sensor die, a glass plate, peripheral spacer, an optical element, an outer surface having a shoulder extending in a direction substantially parallel to the sensor die, and a metal layer at least partially covering the outer surface. A method of manufacturing a camera module includes providing an assembly including a sensor dice wafer, a spacer wafer in front of the sensor dice wafer, and an optical element wafer in front of the spacer wafer. The method includes sawing a top cut, using a first saw blade of a first thickness, proceeding in a direction from the optical element wafer toward the sensor dice wafer, stopping before the sensor dice wafer is reached, and sawing a bottom cut, using a second saw blade of a second thickness, proceeding in a direction from the sensor dice wafer toward the optical element wafer.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Emmanuelle Vigier-Blanc, Jean-Luc Jaffard
  • Publication number: 20120146170
    Abstract: A camera module includes a sensor die, a glass plate, peripheral spacer, an optical element, an outer surface having a shoulder extending in a direction substantially parallel to the sensor die, and a metal layer at least partially covering the outer surface. A method of manufacturing a camera module includes providing an assembly including a sensor dice wafer, a spacer wafer in front of the sensor dice wafer, and an optical element wafer in front of the spacer wafer. The method includes sawing a top cut, using a first saw blade of a first thickness, proceeding in a direction from the optical element wafer toward the sensor dice wafer, stopping before the sensor dice wafer is reached, and sawing a bottom cut, using a second saw blade of a second thickness, proceeding in a direction from the sensor dice wafer toward the optical element wafer.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 14, 2012
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Emmanuelle Vigier-Blanc, Jean-Luc Jaffard
  • Patent number: 6888575
    Abstract: An improved digital cut-off control loop for black level adjustment in a video processor for controlling RGB output signals. The improved circuit advantageously provides a higher resolution of the black level adjustment, and a short cut-off convergence time when the TV set is switched on. The improved circuit can also blank the RGB output when the cut-off control loop has not converged to the correct level.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Yann Desprez-Le Goarant, Jean-Luc Jaffard, Christian Michon
  • Publication number: 20040227068
    Abstract: A method for attaching a sensor and a housing to opposite sides of a mounting substrate is provided. The sensor has a sensing face that includes a sensing area and at least one signal output contact thereon. The mounting substrate has a circuitry face and at least one signal input contact thereon. The mounting substrate also has an opening therethrough. The method includes positioning the sensing area over the opening so that the at least one signal output contact of the sensor makes contact with the at least one signal input contact of the mounting substrate. The mounting substrate receives the housing so that the housing and the sensor are in alignment.
    Type: Application
    Filed: October 2, 2003
    Publication date: November 18, 2004
    Applicant: STMicroelectronics Ltd.
    Inventors: Jeffrey Raynor, Jean-Luc Jaffard
  • Patent number: 5990722
    Abstract: The present invention concerns a transmission circuit of an audio/video data bus that includes a clamp connected between first and second output terminals of the transmission circuit; biasing networks for respectively biasing the output terminals during one operational mode of the transmission circuit; and switched biasing networks for respectively biasing the output terminals during a second operational mode of the transmission circuit; the switched biasing networks being controlled by a digital input signal, wherein a circuit is provided for protecting the clamp from short circuit connections to the transmission circuits voltage supply rails.
    Type: Grant
    Filed: June 24, 1996
    Date of Patent: November 23, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean-Luc Jaffard, Olivier Allain Jean Le Briz
  • Patent number: 5724201
    Abstract: A device for switching a read head from a write mode to a read mode includes a voltage ramp generating circuit, generating and outputting a voltage ramp after a write operation; a variable current source for discharging an initial current of the read head, wherein a current output by the current source is controlled proportionally to the slope between the beginning of the voltage ramp and a first threshold of the ramp, the current source having an initial maximum value higher than the initial current of the head; and an accentuating circuit for accentuating the ramp slope between the beginning of the ramp and a time when the current output by the variable current source becomes equal to the initial current present in the head.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: March 3, 1998
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean-Luc Jaffard, Yann Desprez-Le Goarant
  • Patent number: 5508656
    Abstract: A signal processing circuit that includes a differential amplifier and an integrator. The differential amplifier receives at a first input a signal to process and at a second input an offset compensation signal provided by the integrator. The integrator includes a differential transconductance amplifier receiving an output voltage of the signal processing circuit at a first input and a reference voltage at a second input; a capacitor having a first terminal connected to the output of the transconductance amplifier and a second terminal connected to a fixed voltage; and a voltage follower receiving the voltage at the first terminal of the capacitor and providing the offset compensation signal.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: April 16, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean-Luc Jaffard, Randolph Fox
  • Patent number: 5483390
    Abstract: A device for switching a read head from a write mode to a read mode includes a voltage ramp generating circuit, generating and outputting a voltage ramp after a write operation; a variable current source for discharging an initial current of the read head, wherein a current output by the current source is controlled proportionally to the slope between the beginning of the voltage ramp and a first threshold of the ramp, the current source having an initial maximum value higher than the initial current of the head; and an accentuating circuit for accentuating the ramp slope between the beginning of the ramp and a time when the current output by the variable current source becomes equal to the initial current present in the head.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: January 9, 1996
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Jean-Luc Jaffard, Yann Desprez-Le Goarant
  • Patent number: 5381277
    Abstract: A device for switching from the write mode to the read mode includes a read head connected between a first and a second input terminal of the differential amplifier, the second input terminal being connected to a constant voltage through a capacitor and to the amplifier output through the resistor. The apparatus includes a circuit for generating a voltage ramp, after a write operation; a circuit for discharging an initial current in the read head proportionally to the voltage ramp between the beginning of the ramp and a first threshold voltage of the ramp; a switch for shorting the resistor to a low value, at least between the first threshold voltage and a second ramp threshold voltage; and a detector for detecting the second threshold voltage and for providing, in the vicinity of the threshold, a progressive control of the switch.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: January 10, 1995
    Assignee: SGS-Thompson Microelectronics S.A.
    Inventors: Jean-Luc Jaffard, Yann Desprez-Le Goarant
  • Patent number: 5189685
    Abstract: A counter/divider dividing an input frequency (F1) by 2.sup.q+n +1/2, comprises a first divider by 2.sup.q (30) receiving the signal to divide of a frequency F1 and provides 2.sup.q+1 outputs at the frequency F1/2.sup.q out of phase the ones to the others of 360.degree./2.sup.q+1 ; a multiplexer (32) having a control terminal (34) and sequentially providng at its output (33) each of said 2.sup.q+1 outputs each time a control signal is applied; and a second divider by 2.sup.n (31) receiving the output (33) of the multiplexer and providing the desired output (34) of the counter/divider, this output being applied to the control terminal of the multiplexer.
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: February 23, 1993
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Jean-Luc Jaffard, Loic Lietar, Michel Mouret
  • Patent number: 5164864
    Abstract: A comparison circuit associated with a video tape recorder having two identical legs (41, 42), one of which (41) is connected to a head of a first type and the other (42) to a head of a second type, the outputs of both being connected to a respective input of a comparison means (56) for selecting in "search" mode the head which presents the highest signal amplitude. Each branch comprises, in series, a high-pass filter (45), a variable gain amplifier (46), a multiplier (47), a low-pass filter (48) and a capacitance amplifier (49).
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: November 17, 1992
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Philippe Perroud, Jean-Luc Jaffard
  • Patent number: 5045810
    Abstract: A broadband amplifier comprises a bipolar transistor (T), having a base connected to the input terminal (2), a collector connected to the output terminal (3) which is in turn connected to a supply source (11) through a first resistor (R1), and an emitter grounded. A second resistor (R2), the value of which varies simultaneously with the current gain (.beta.) of the transistor is connected between the output terminal and the transistor base. This broadband amplifier further comprises a capacitor (C) connected in parallel across the terminals of the second resistor and a third resistor (R3) connected between the second resistor and the transistor base.
    Type: Grant
    Filed: June 22, 1990
    Date of Patent: September 3, 1991
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Philippe Perroud, Jean-Luc Jaffard
  • Patent number: 5045803
    Abstract: A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an additional amplifier (A1, A2), and an additional resistor (R2a, R2b), respectively. The inputs of the additional amplifiers being connected to ground through a common resistor (R) and to the emitters of the two transistors through a common resistor (R1). Each sub-circuit further comprises a second switch (K2) formed by a single transistor.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: September 3, 1991
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Philippe Perroud, Jean-Luc Jaffard
  • Patent number: RE35305
    Abstract: A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an additional amplifier (A1, A2), and an additional resistor (R2a, R2b), respectively. The inputs of the additional amplifiers being connected to ground through a common resistor (R) and to the emitters of the two transistors through a common resistor (R1). Each sub-circuit further comprises a second switch (K2) formed by a single transistor.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: July 30, 1996
    Assignee: SGS-Thomson Microelectronics, S.A.
    Inventors: Philippe Perroud, Jean-Luc Jaffard