Abstract: A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source and drain electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein: the gate recess width (Wri) and the gate length (LGo) are manufactured with predetermined respective values, in order that the access region, defined between the gate (G) and the gate recess edge (31), has an access region width (2&Dgr;o), derived from said predetermined values (Wri, LGo), which is sufficiently small to permit the transistor of functioning according to saturation current characteristics having continuous slopes.

Abstract: A process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of semiconductor layers on a substrate including an active layer (3), forming a recess in said active layer, referred to as gate recess (A4), for constituting a channel between source and drain electrodes, and forming a submicronic gate electrode (G) which is in contact with the active layer (3) in said gate recess (A4), wherein:

Abstract: A process of manufacturing a semiconductor device with a double-recessed gate field effect transistor, comprising the formation, on a substrate (1), of an active layer (3) of a semiconductor material and a first dielectric layer (D1), and further comprising the steps of: forming a second dielectric layer (R), forming an aperture (A0) in the second dielectric layer (R), then a first opening (A1) in the first dielectric layer (D1) having a same first width, while forming a second opening (A2) in the second dielectric layer having a second width larger than the first width, and then etching a preliminary recess (A4) in the subjacent semiconductor layer through said first opening (A1) having said first width, enlarging said first opening (A1) in the first dielectric layer (D1) to form a third opening (A3) having a third width larger than the second width, and then etching the semiconductor layer through said preliminary recess (A4) to form a deeper central recess (A6) having substantially said first width while