Abstract: An error correction device for digital data storage and transfer systems wherein data are transferred over a plurality of channels. Synchronously with the transfer of a group of data bits, a coding device forms a first correction bit for a first correction channel and a second correction bit for a second correction channel. The first correction bit is formed on the basis of a second group of data bits, the second correction bits being formed on the basis of a third group of data bits. Each data channel supplies the data of two sub-groups of data bits for this purpose. The delay operator having a length of one bit cell being represented by D, a series of directly successive bits can be represented by a polynomial in D: x0.D.sup.0 +x1.D.sup.1 +x2.D.sup.2 + . . ., in which xj (j =0, 1 . . .) represents the bit value.