Abstract: Techniques and systems for test case selection and ordering with covert minimum set cover for functional qualification are described. Some embodiments can determine a first set of test cases by, iteratively, identifying a set of faults that is covered by a smallest set of test cases, determining whether or not a test case that covers a fault is able to detect the fault, and selecting and adding a test case to the first set of test cases. Next, the embodiments can execute a minimum set cover process on the first set of test cases by using coverage scores for test cases in the first set of test cases for ranking.

Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.

Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.