Abstract: The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.

Abstract: Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.

Abstract: Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.

Abstract: A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.