Abstract: An apparatus and method for using self-timing logic to make at least two accesses to a memory core in one clock cycle is disclosed. In one embodiment of the invention, a memory wrapper (28) incorporating self-timing logic (36) and a mux (32) is used to couple a single access memory core (30) to a memory interface unit (10). The memory interface unit (10) couples a central processing unit (12) to the memory wrapper (28). The self-timing architecture as applied to multi-access memory wrappers avoids the need for calibration. Moreover, the self-timing architecture provides for a full dissociation between the environment (what is clocked on the system clock) and the access to the core. A beneifical result of the invention is making access at the speed of the core while processing several access in one system clock cycle.