Abstract: A packet scheduling system for use in a switching node of a high speed packet switching network. Incoming packets are enqueued in connection queues. Each connection is classified as red (exceeding traffic profile) or green (within traffic profile). QOS priority is also identified for each connection. Packets are dequeued for transmission as a function of priority class and connection class. Higher priority class connections have priority over lower priority class connections. Within a given priority class of connections, green connections have priority over red connections. Round robin scheduling is used for packets from connections in the same priority and connection class. In addition, a dynamic priority coupling mechanism is provided to prevent red higher priority traffic from blocking green lower priority traffic.

Abstract: A method and an apparatus for searching a bit field whose significant bits comprise two contiguous bit fields such as the VPI/VCI bit fields of an ATM cell header. The invention uses a hash key based on CRC-n calculated on the bit field to be searched. One m bit field part of the significant bits of the bit field to be searched can be concatenated with the CRC-n to form a double hash key. It appears that, L being the total of the two contiguous bit field lengths, if L=m=n+p, p being greater or equal to 4, the scattering of data to be searched is perfect. The method comprised a first step of pointing to a first address with the hash (or double hash) key and reading a maximum of 2.sup.p addresses before reaching the addresses containing the bit field to be searched.

Abstract: A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound timer as respective numbers A and B coded in a 2's-complement form. Relative date discrimination is implemented by dividing the wraparound timer period into four consecutive intervals, each defined by the two most significant bits of the timer count. The value of the most significant bits and the sign of A-B, are used to derive a one-bit "X" indicator, the binary value of which indicates which of the two dates d1 and d2 was first to occur.

Abstract: Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased).

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprisesmeans for buffering (132) said data packets,means for identifying said buffering means and said data packets in said buffering means,means for queueing (FIG. 15) in storing means (131) said identifying means in a single instruction,means for dequeueing (FIG. 16) from said storing (131) means said identifying means in another single instruction,means for releasing said buffering means,Each instruction comprises up to three operations executed in parallel by said processing means:an arithmetical and logical (ALU) operation on said identifying means,memory operation on said storing means, anda sequence operation.

Abstract: An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.

Abstract: A device for interconnecting source users and destination users includes a common bus to which a memory with a plurality of independent buffers, a memory interface (22) and a central control apparatus (26) are connected. The memory interface (22) receives messages from source users, stores the messages in selected buffers and chains the buffers together. The central control apparatus generates inbound message queues and outbound message queues in response to commands which it receives from the memory interface.

Abstract: In a shared memory system, wherein several memory users MU wish access to a plurality of memory banks, a set of high level commands (CREATE, PUT, GET, RELEASE) is provided, to transfer data between a given memory user and the memory banks or another memory user. The high level commands sent by the memory users are built up by memory interfaces MI connected to the memory users, and transmitted through an interconnection network to Packet Memory Command Executors PMCE integrated into each memory bank. The high level commands work with data records identified by Logical Record Addresses (LRA) known by the memory users. During execution of the high level commands by the PMCE, the LRA are translated into physical addresses corresponding to physical address space in the memory banks. The physical address space is created dynamically and released upon need, through the Create or Release Commands.

Abstract: An interface and protocol for linking devices (18) with a control unit (10). The interface includes a dedicated request line (30) per device, a dot-ORed acknowledge line (32), at least one clock line (38) transmitting sets of N clock pulses from the control unit to a device during each data exchange, two data line (34, 36) for serial duplex data transmission and a pair of shift registers one being positioned in the control unit and another being positioned in each of the devices. The protocol is such that for either a read or a write operation the control unit issues two request signals in spaced relationship on the request line and the selected device responds with two acknowledge signals is spaced relationship on the acknowledge line with each one of the acknowledge signals falling after the fall of its associated request signal.

Abstract: An error detection apparatus is implemented in a passive device inserted on a synchronous bus, linking two devices. The bus has data lines onto which data are transferred between the two devices under control of tag lines and clock signals which are companion of the transferred data. The apparatus allows errors to be detected, the failing device to be identified and the error signals to be reported in a psuedo-synchronous way on an error bus due to error detection and reporting logic circuits and a pseudo-synchronous timing circuit.

Abstract: An arbitration device for enabling a common resource to be shared by a plurality of processors, all connected by a common bus and each processor having a certain access priority. When more than one processor requests access to the resource, the highest priority processor request signal is latched and access is granted while the other requesting processor's latches remain set (access not granted). If two processors request access while the resource is busy, then only the latch of the processor having the highest priority of the two will be reset when the bus becomes available, and that processor will gain access.

Abstract: The contents of input time-division channels on a closed-loop link (10LO, 10HI) are stored in a memory (173) at the address supplied by an input address counter (IAC) controlled by an incoming timing signal (2MCR). The memory is read out under control of an output address counter (OAC) controlled by an outgoing timing signal (2MCT). Each time interval is divided into one read period and two write periods. Means (186) are provided to select one of the two write periods dependent on the phase relationship between the incoming and outgoing timing signals. The units connected in series by means of the closed-loop link receive a timing signal circulating on a timing loop (15) that is closed by a master timing device (13). Slave timing devices (18) inserted in the timing loop regenerate the timing signals circulating thereon and check same.