Patents by Inventor Jean-Marie Quoc Danh TRAN

Jean-Marie Quoc Danh TRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10915490
    Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 9, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Neven Klacar, Murali Krishna, Arunn Coimbatore Krishnamurthy, Jitendra Prasad, Jean-Marie Quoc Danh Tran
  • Publication number: 20190251056
    Abstract: Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 15, 2019
    Inventors: Neven Klacar, Murali Krishna, Arunn Coimbatore Krishnamurthy, Jitendra Prasad, Jean-Marie Quoc Danh Tran
  • Publication number: 20160196231
    Abstract: Various embodiments of methods and systems for managing bus bandwidth allocation in a system on a chip are disclosed. Certain embodiments monitor a high speed bus for a measurement window of time to identify valid bits uniquely associated with transaction requests issued by a master processing engine. The method continues to monitor the bus over the window to identify completed transactions. A latency value is calculated by subtracting a target latency from an actual latency for each completed transaction. The latency value is aggregated in a counter. At the conclusion of the window, if the aggregated latency value is positive, the method may conclude that the average latency per transaction over the window exceeded the target latency per transaction and that the bandwidth allocated to the engine should be increased.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 7, 2016
    Inventors: NHON TOAI QUACH, JEAN-MARIE QUOC DANH TRAN, NIKOLAI SCHLEGEL, JEAN-LOUIS TARDIEUX, BING XIAO
  • Patent number: 9204437
    Abstract: Techniques and apparatus are provided for conditional offload of one or more LLRs or decoded bits. An exemplary electronic device (ED) method includes receiving a transmission of a physical downlink shared channel (PDSCH) having a transport block (TB) comprising at least one code block (CB), performing a cyclic redundancy check (CRC) of the at least one CB, in a memory external to a modem core of the ED, storing a subset of log-likelihood ratios (LLRs) associated with the at least one CB if the at least one CB failed the CRC or decoded bits associated with the at least one CB if the at least one CB passed the CRC, wherein the subset is based on an LLR range of the transmission relative to an LLR range of one or more previous transmissions, and using the stored subset of LLRs or decoded bits to process a re-transmission of the PDSCH.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: December 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: John Edward Smee, Jean-Marie Quoc Danh Tran, Michael Lee McCloud, Peter John Black, Alexei Yurievitch Gorokhov
  • Publication number: 20140241269
    Abstract: Techniques and apparatus are provided for conditional offload of one or more LLRs or decoded bits. An exemplary electronic device (ED) method includes receiving a transmission of a physical downlink shared channel (PDSCH) having a transport block (TB) comprising at least one code block (CB), performing a cyclic redundancy check (CRC) of the at least one CB, in a memory external to a modem core of the ED, storing a subset of log-likelihood ratios (LLRs) associated with the at least one CB if the at least one CB failed the CRC or decoded bits associated with the at least one CB if the at least one CB passed the CRC, wherein the subset is based on an LLR range of the transmission relative to an LLR range of one or more previous transmissions, and using the stored subset of LLRs or decoded bits to process a re-transmission of the PDSCH.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 28, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: John Edward SMEE, Jean-Marie Quoc Danh TRAN, Michael Lee MCCLOUD, Peter John BLACK, Alexei Yurievitch GOROKHOV