Patents by Inventor Jean-Michel Gril-Maffre
Jean-Michel Gril-Maffre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550377Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.Type: GrantFiled: August 6, 2021Date of Patent: January 10, 2023Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Herve Cassagnes, Cyril Moulin, Jean-Michel Gril-Maffre
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Patent number: 11495275Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.Type: GrantFiled: June 2, 2021Date of Patent: November 8, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Christophe Eva, Jean-Michel Gril-Maffre
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Publication number: 20220066524Abstract: Integrated circuit, method for resetting and computer program product. The integrated circuit comprises a first portion and a second portion. The first portion comprises a reset input configured to receive a reset signal, an activation module connected to the reset input. The activation module is configured to activate the second portion upon reception of the reset signal. The first portion comprises an emissions module configured to emit a replicated reset signal. The second portion can be selectively activated or deactivated. The second portion comprises a reset input configured to receive the replicated reset signal of the emissions module, a determination module configured to determine that an elapsed time starting from the activation of the second portion of the circuit oversteps a threshold.Type: ApplicationFiled: August 6, 2021Publication date: March 3, 2022Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Herve CASSAGNES, Cyril MOULIN, Jean-Michel GRIL-MAFFRE
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Publication number: 20210390990Abstract: A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.Type: ApplicationFiled: June 2, 2021Publication date: December 16, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Christophe EVA, Jean-Michel GRIL-MAFFRE
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Patent number: 11189360Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.Type: GrantFiled: October 30, 2019Date of Patent: November 30, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Jean-Michel Gril-Maffre, Christophe Eva
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Patent number: 11120887Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.Type: GrantFiled: November 12, 2020Date of Patent: September 14, 2021Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Christophe Eva, Jean-Michel Gril-Maffre
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Publication number: 20210158887Abstract: An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.Type: ApplicationFiled: November 12, 2020Publication date: May 27, 2021Inventors: Christophe Eva, Jean-Michel Gril-Maffre
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Patent number: 10719331Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: GrantFiled: July 3, 2018Date of Patent: July 21, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Publication number: 20200174927Abstract: A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.Type: ApplicationFiled: October 30, 2019Publication date: June 4, 2020Inventors: Jean-Michel Gril-Maffre, Christophe Eva
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Publication number: 20180329721Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Publication number: 20170147362Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.Type: ApplicationFiled: May 12, 2016Publication date: May 25, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Nicolas Froidevaux, Jean-Michel Gril-Maffre, Jean-Pierre Leca
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Patent number: 7421595Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.Type: GrantFiled: March 17, 2005Date of Patent: September 2, 2008Assignee: STMicroelectronics S.A.Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
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Publication number: 20050216779Abstract: A microprocessor includes a computation unit for executing operations respectively associated with instructions of a determined set of instructions of the microprocessor. A control unit interprets the instructions and controls the computation unit accordingly. The microprocessor further includes a blocking unit which is controlled by the control unit in response to the execution of a standby instruction belonging to the set of instructions for placing the microprocessor in a standby state during an undetermined period. The exit of the microprocessor from the standby state is conditioned by a determined value or a determined change of the value of a condition bit stored in a condition register, which is internal or external to the microprocessor.Type: ApplicationFiled: March 16, 2005Publication date: September 29, 2005Applicant: STMicroelectronics S.A.Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
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Publication number: 20050216704Abstract: A microprocessor has a set of determined instructions which are coded on a determined number P of bits in an instruction coding space of size 2{circumflex over (?)}P. The microprocessor includes a mode register having a determined number N of mode bits. A further included decoding unit and an execution unit are arranged so as to decode and execute a given instruction (Ii) according to at least one first or one second mode of execution as a function of the values of a determined number Qi of mode bits associated with the instruction. The instruction corresponds to distinct respective operations in the first mode of execution and in the second mode of execution where Qi is a strictly positive integer.Type: ApplicationFiled: March 17, 2005Publication date: September 29, 2005Applicant: STMicroelectronics S.A.Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
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Publication number: 20050216778Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.Type: ApplicationFiled: March 17, 2005Publication date: September 29, 2005Applicant: STMicroelectronics S.A.Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre